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lukel97DanielCChen
lukel97
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[RISCV] Remove {s,u}int_to_fp custom op action for f16/bf16 (llvm#111471)
It turns out that {s,u}int_to_fp nodes get their operation action from their operand's type, not the result type, so we don't need to set it for fp16 or bf16. vp_{s,u}int_to_fp uses the result type though so we need to keep it. This also means that we can lower int_to_fp for fixed length bf16 vectors already, so this adds tests for that. The cost model test changes are due to BasicTTIImpl's getCastInstrCost not taking into account that int_to_fp needs its legal type swapped. This can be fixed in a later patch, but its worth noting that the affected types in the tests currently crash when lowered anyway (due to them needing split at LMUL > 8)
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4 files changed

+189
-18
lines changed

4 files changed

+189
-18
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 3 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,9 +1071,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
10711071
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
10721072
Custom);
10731073
setOperationAction(ISD::SELECT_CC, VT, Expand);
1074-
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP, ISD::VP_SINT_TO_FP,
1075-
ISD::VP_UINT_TO_FP},
1076-
VT, Custom);
1074+
setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
10771075
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS,
10781076
ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR,
10791077
ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE,
@@ -1343,9 +1341,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
13431341
setOperationAction(
13441342
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
13451343
Custom);
1346-
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP,
1347-
ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP},
1348-
VT, Custom);
1344+
setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT,
1345+
Custom);
13491346
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
13501347
if (Subtarget.hasStdExtZfhmin()) {
13511348
setOperationAction(ISD::BUILD_VECTOR, VT, Custom);

‎llvm/test/Analysis/CostModel/RISCV/cast-half.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -842,7 +842,7 @@ define void @sitofp() {
842842
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v64i64_v64f16 = sitofp <64 x i64> undef to <64 x half>
843843
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %v64i1_v64f16 = sitofp <64 x i1> undef to <64 x half>
844844
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %v128i8_v128f16 = sitofp <128 x i8> undef to <128 x half>
845-
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i16_v128f16 = sitofp <128 x i16> undef to <128 x half>
845+
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v128i16_v128f16 = sitofp <128 x i16> undef to <128 x half>
846846
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v128i32_v128f16 = sitofp <128 x i32> undef to <128 x half>
847847
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %v128i64_v128f16 = sitofp <128 x i64> undef to <128 x half>
848848
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %v128i1_v128f16 = sitofp <128 x i1> undef to <128 x half>
@@ -988,7 +988,7 @@ define void @sitofp() {
988988
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v64i64_v64f16 = sitofp <64 x i64> undef to <64 x half>
989989
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %v64i1_v64f16 = sitofp <64 x i1> undef to <64 x half>
990990
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %v128i8_v128f16 = sitofp <128 x i8> undef to <128 x half>
991-
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i16_v128f16 = sitofp <128 x i16> undef to <128 x half>
991+
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v128i16_v128f16 = sitofp <128 x i16> undef to <128 x half>
992992
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v128i32_v128f16 = sitofp <128 x i32> undef to <128 x half>
993993
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %v128i64_v128f16 = sitofp <128 x i64> undef to <128 x half>
994994
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %v128i1_v128f16 = sitofp <128 x i1> undef to <128 x half>
@@ -1208,7 +1208,7 @@ define void @uitofp() {
12081208
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v64i64_v64f16 = uitofp <64 x i64> undef to <64 x half>
12091209
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %v64i1_v64f16 = uitofp <64 x i1> undef to <64 x half>
12101210
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %v128i8_v128f16 = uitofp <128 x i8> undef to <128 x half>
1211-
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i16_v128f16 = uitofp <128 x i16> undef to <128 x half>
1211+
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v128i16_v128f16 = uitofp <128 x i16> undef to <128 x half>
12121212
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v128i32_v128f16 = uitofp <128 x i32> undef to <128 x half>
12131213
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %v128i64_v128f16 = uitofp <128 x i64> undef to <128 x half>
12141214
; RV32ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %v128i1_v128f16 = uitofp <128 x i1> undef to <128 x half>
@@ -1354,7 +1354,7 @@ define void @uitofp() {
13541354
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %v64i64_v64f16 = uitofp <64 x i64> undef to <64 x half>
13551355
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 49 for instruction: %v64i1_v64f16 = uitofp <64 x i1> undef to <64 x half>
13561356
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %v128i8_v128f16 = uitofp <128 x i8> undef to <128 x half>
1357-
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %v128i16_v128f16 = uitofp <128 x i16> undef to <128 x half>
1357+
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 66 for instruction: %v128i16_v128f16 = uitofp <128 x i16> undef to <128 x half>
13581358
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 50 for instruction: %v128i32_v128f16 = uitofp <128 x i32> undef to <128 x half>
13591359
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 54 for instruction: %v128i64_v128f16 = uitofp <128 x i64> undef to <128 x half>
13601360
; RV64ZVFHMIN-NEXT: Cost Model: Found an estimated cost of 99 for instruction: %v128i1_v128f16 = uitofp <128 x i1> undef to <128 x half>

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

Lines changed: 62 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
3-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
4-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
5-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
2+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
3+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
4+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
5+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
66

77
define void @fp2si_v2f32_v2i32(ptr %x, ptr %y) {
88
; CHECK-LABEL: fp2si_v2f32_v2i32:
@@ -432,6 +432,64 @@ define void @fp2ui_v8f32_v8i64(ptr %x, ptr %y) {
432432
ret void
433433
}
434434

435+
define void @fp2si_v2bf16_v2i64(ptr %x, ptr %y) {
436+
; CHECK-LABEL: fp2si_v2bf16_v2i64:
437+
; CHECK: # %bb.0:
438+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
439+
; CHECK-NEXT: vle16.v v8, (a0)
440+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
441+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
442+
; CHECK-NEXT: vfwcvt.rtz.x.f.v v8, v9
443+
; CHECK-NEXT: vse64.v v8, (a1)
444+
; CHECK-NEXT: ret
445+
%a = load <2 x bfloat>, ptr %x
446+
%d = fptosi <2 x bfloat> %a to <2 x i64>
447+
store <2 x i64> %d, ptr %y
448+
ret void
449+
}
450+
451+
define void @fp2ui_v2bf16_v2i64(ptr %x, ptr %y) {
452+
; CHECK-LABEL: fp2ui_v2bf16_v2i64:
453+
; CHECK: # %bb.0:
454+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
455+
; CHECK-NEXT: vle16.v v8, (a0)
456+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
457+
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
458+
; CHECK-NEXT: vfwcvt.rtz.xu.f.v v8, v9
459+
; CHECK-NEXT: vse64.v v8, (a1)
460+
; CHECK-NEXT: ret
461+
%a = load <2 x bfloat>, ptr %x
462+
%d = fptoui <2 x bfloat> %a to <2 x i64>
463+
store <2 x i64> %d, ptr %y
464+
ret void
465+
}
466+
467+
define <2 x i1> @fp2si_v2bf16_v2i1(<2 x bfloat> %x) {
468+
; CHECK-LABEL: fp2si_v2bf16_v2i1:
469+
; CHECK: # %bb.0:
470+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
471+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
472+
; CHECK-NEXT: vfncvt.rtz.x.f.w v8, v9
473+
; CHECK-NEXT: vand.vi v8, v8, 1
474+
; CHECK-NEXT: vmsne.vi v0, v8, 0
475+
; CHECK-NEXT: ret
476+
%z = fptosi <2 x bfloat> %x to <2 x i1>
477+
ret <2 x i1> %z
478+
}
479+
480+
define <2 x i1> @fp2ui_v2bf16_v2i1(<2 x bfloat> %x) {
481+
; CHECK-LABEL: fp2ui_v2bf16_v2i1:
482+
; CHECK: # %bb.0:
483+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
484+
; CHECK-NEXT: vfwcvtbf16.f.f.v v9, v8
485+
; CHECK-NEXT: vfncvt.rtz.xu.f.w v8, v9
486+
; CHECK-NEXT: vand.vi v8, v8, 1
487+
; CHECK-NEXT: vmsne.vi v0, v8, 0
488+
; CHECK-NEXT: ret
489+
%z = fptoui <2 x bfloat> %x to <2 x i1>
490+
ret <2 x i1> %z
491+
}
492+
435493
define void @fp2si_v2f16_v2i64(ptr %x, ptr %y) {
436494
; CHECK-LABEL: fp2si_v2f16_v2i64:
437495
; CHECK: # %bb.0:

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

Lines changed: 120 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
3-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
4-
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
5-
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
2+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH32
3+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfh,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFH,ZVFH64
4+
; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN32
5+
; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+zvfhmin,+zvfbfmin,+f,+d -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,ZVFHMIN,ZVFHMIN64
66

77
define void @si2fp_v2i32_v2f32(ptr %x, ptr %y) {
88
; CHECK-LABEL: si2fp_v2i32_v2f32:
@@ -418,6 +418,122 @@ define <8 x double> @ui2fp_v8i1_v8f64(<8 x i1> %x) {
418418
ret <8 x double> %z
419419
}
420420

421+
define void @si2fp_v2i64_v2bf16(ptr %x, ptr %y) {
422+
; CHECK-LABEL: si2fp_v2i64_v2bf16:
423+
; CHECK: # %bb.0:
424+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
425+
; CHECK-NEXT: vle64.v v8, (a0)
426+
; CHECK-NEXT: vfncvt.f.x.w v9, v8
427+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
428+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
429+
; CHECK-NEXT: vse16.v v8, (a1)
430+
; CHECK-NEXT: ret
431+
%a = load <2 x i64>, ptr %x
432+
%d = sitofp <2 x i64> %a to <2 x bfloat>
433+
store <2 x bfloat> %d, ptr %y
434+
ret void
435+
}
436+
437+
define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
438+
; CHECK-LABEL: ui2fp_v2i64_v2bf16:
439+
; CHECK: # %bb.0:
440+
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
441+
; CHECK-NEXT: vle64.v v8, (a0)
442+
; CHECK-NEXT: vfncvt.f.xu.w v9, v8
443+
; CHECK-NEXT: vsetvli zero, zero, e16, mf4, ta, ma
444+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
445+
; CHECK-NEXT: vse16.v v8, (a1)
446+
; CHECK-NEXT: ret
447+
%a = load <2 x i64>, ptr %x
448+
%d = uitofp <2 x i64> %a to <2 x bfloat>
449+
store <2 x bfloat> %d, ptr %y
450+
ret void
451+
}
452+
453+
define <2 x bfloat> @si2fp_v2i1_v2bf16(<2 x i1> %x) {
454+
; CHECK-LABEL: si2fp_v2i1_v2bf16:
455+
; CHECK: # %bb.0:
456+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
457+
; CHECK-NEXT: vmv.v.i v8, 0
458+
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
459+
; CHECK-NEXT: vfwcvt.f.x.v v9, v8
460+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
461+
; CHECK-NEXT: ret
462+
%z = sitofp <2 x i1> %x to <2 x bfloat>
463+
ret <2 x bfloat> %z
464+
}
465+
466+
define <2 x bfloat> @ui2fp_v2i1_v2bf16(<2 x i1> %x) {
467+
; CHECK-LABEL: ui2fp_v2i1_v2bf16:
468+
; CHECK: # %bb.0:
469+
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
470+
; CHECK-NEXT: vmv.v.i v8, 0
471+
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
472+
; CHECK-NEXT: vfwcvt.f.xu.v v9, v8
473+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v9
474+
; CHECK-NEXT: ret
475+
%z = uitofp <2 x i1> %x to <2 x bfloat>
476+
ret <2 x bfloat> %z
477+
}
478+
479+
define void @si2fp_v8i64_v8bf16(ptr %x, ptr %y) {
480+
; CHECK-LABEL: si2fp_v8i64_v8bf16:
481+
; CHECK: # %bb.0:
482+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
483+
; CHECK-NEXT: vle64.v v8, (a0)
484+
; CHECK-NEXT: vfncvt.f.x.w v12, v8
485+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
486+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
487+
; CHECK-NEXT: vse16.v v8, (a1)
488+
; CHECK-NEXT: ret
489+
%a = load <8 x i64>, ptr %x
490+
%d = sitofp <8 x i64> %a to <8 x bfloat>
491+
store <8 x bfloat> %d, ptr %y
492+
ret void
493+
}
494+
495+
define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
496+
; CHECK-LABEL: ui2fp_v8i64_v8bf16:
497+
; CHECK: # %bb.0:
498+
; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma
499+
; CHECK-NEXT: vle64.v v8, (a0)
500+
; CHECK-NEXT: vfncvt.f.xu.w v12, v8
501+
; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma
502+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v12
503+
; CHECK-NEXT: vse16.v v8, (a1)
504+
; CHECK-NEXT: ret
505+
%a = load <8 x i64>, ptr %x
506+
%d = uitofp <8 x i64> %a to <8 x bfloat>
507+
store <8 x bfloat> %d, ptr %y
508+
ret void
509+
}
510+
511+
define <8 x bfloat> @si2fp_v8i1_v8bf16(<8 x i1> %x) {
512+
; CHECK-LABEL: si2fp_v8i1_v8bf16:
513+
; CHECK: # %bb.0:
514+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
515+
; CHECK-NEXT: vmv.v.i v8, 0
516+
; CHECK-NEXT: vmerge.vim v8, v8, -1, v0
517+
; CHECK-NEXT: vfwcvt.f.x.v v10, v8
518+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
519+
; CHECK-NEXT: ret
520+
%z = sitofp <8 x i1> %x to <8 x bfloat>
521+
ret <8 x bfloat> %z
522+
}
523+
524+
define <8 x bfloat> @ui2fp_v8i1_v8bf16(<8 x i1> %x) {
525+
; CHECK-LABEL: ui2fp_v8i1_v8bf16:
526+
; CHECK: # %bb.0:
527+
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
528+
; CHECK-NEXT: vmv.v.i v8, 0
529+
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0
530+
; CHECK-NEXT: vfwcvt.f.xu.v v10, v8
531+
; CHECK-NEXT: vfncvtbf16.f.f.w v8, v10
532+
; CHECK-NEXT: ret
533+
%z = uitofp <8 x i1> %x to <8 x bfloat>
534+
ret <8 x bfloat> %z
535+
}
536+
421537
define void @si2fp_v2i64_v2f16(ptr %x, ptr %y) {
422538
; CHECK-LABEL: si2fp_v2i64_v2f16:
423539
; CHECK: # %bb.0:

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