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Revert "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (llvm#112200)
Reverts llvm#111774 This appears to be causing some tests to fail.
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‎llvm/include/llvm/CodeGen/SDPatternMatch.h

Lines changed: 0 additions & 99 deletions
Original file line numberDiff line numberDiff line change
@@ -542,81 +542,6 @@ struct BinaryOpc_match {
542542
}
543543
};
544544

545-
template <typename LHS_P, typename RHS_P, typename Pred_t,
546-
bool Commutable = false, bool ExcludeChain = false>
547-
struct MaxMin_match {
548-
using PredType = Pred_t;
549-
LHS_P LHS;
550-
RHS_P RHS;
551-
552-
MaxMin_match(const LHS_P &L, const RHS_P &R) : LHS(L), RHS(R) {}
553-
554-
template <typename MatchContext>
555-
bool match(const MatchContext &Ctx, SDValue N) {
556-
if (sd_context_match(N, Ctx, m_Opc(ISD::SELECT)) ||
557-
sd_context_match(N, Ctx, m_Opc(ISD::VSELECT))) {
558-
EffectiveOperands<ExcludeChain> EO_SELECT(N, Ctx);
559-
assert(EO_SELECT.Size == 3);
560-
SDValue Cond = N->getOperand(EO_SELECT.FirstIndex);
561-
SDValue TrueValue = N->getOperand(EO_SELECT.FirstIndex + 1);
562-
SDValue FalseValue = N->getOperand(EO_SELECT.FirstIndex + 2);
563-
564-
if (sd_context_match(Cond, Ctx, m_Opc(ISD::SETCC))) {
565-
EffectiveOperands<ExcludeChain> EO_SETCC(Cond, Ctx);
566-
assert(EO_SETCC.Size == 3);
567-
SDValue L = Cond->getOperand(EO_SETCC.FirstIndex);
568-
SDValue R = Cond->getOperand(EO_SETCC.FirstIndex + 1);
569-
auto *CondNode =
570-
cast<CondCodeSDNode>(Cond->getOperand(EO_SETCC.FirstIndex + 2));
571-
572-
if ((TrueValue != L || FalseValue != R) &&
573-
(TrueValue != R || FalseValue != L)) {
574-
return false;
575-
}
576-
577-
ISD::CondCode Cond =
578-
TrueValue == L ? CondNode->get()
579-
: getSetCCInverse(CondNode->get(), L.getValueType());
580-
if (!Pred_t::match(Cond)) {
581-
return false;
582-
}
583-
return (LHS.match(Ctx, L) && RHS.match(Ctx, R)) ||
584-
(Commutable && LHS.match(Ctx, R) && RHS.match(Ctx, L));
585-
}
586-
}
587-
588-
return false;
589-
}
590-
};
591-
592-
// Helper class for identifying signed max predicates.
593-
struct smax_pred_ty {
594-
static bool match(ISD::CondCode Cond) {
595-
return Cond == ISD::CondCode::SETGT || Cond == ISD::CondCode::SETGE;
596-
}
597-
};
598-
599-
// Helper class for identifying unsigned max predicates.
600-
struct umax_pred_ty {
601-
static bool match(ISD::CondCode Cond) {
602-
return Cond == ISD::CondCode::SETUGT || Cond == ISD::CondCode::SETUGE;
603-
}
604-
};
605-
606-
// Helper class for identifying signed min predicates.
607-
struct smin_pred_ty {
608-
static bool match(ISD::CondCode Cond) {
609-
return Cond == ISD::CondCode::SETLT || Cond == ISD::CondCode::SETLE;
610-
}
611-
};
612-
613-
// Helper class for identifying unsigned min predicates.
614-
struct umin_pred_ty {
615-
static bool match(ISD::CondCode Cond) {
616-
return Cond == ISD::CondCode::SETULT || Cond == ISD::CondCode::SETULE;
617-
}
618-
};
619-
620545
template <typename LHS, typename RHS>
621546
inline BinaryOpc_match<LHS, RHS> m_BinOp(unsigned Opc, const LHS &L,
622547
const RHS &R) {
@@ -688,45 +613,21 @@ inline BinaryOpc_match<LHS, RHS, true> m_SMin(const LHS &L, const RHS &R) {
688613
return BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R);
689614
}
690615

691-
template <typename LHS, typename RHS>
692-
inline auto m_SMinLike(const LHS &L, const RHS &R) {
693-
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::SMIN, L, R),
694-
MaxMin_match<LHS, RHS, smin_pred_ty, true>(L, R));
695-
}
696-
697616
template <typename LHS, typename RHS>
698617
inline BinaryOpc_match<LHS, RHS, true> m_SMax(const LHS &L, const RHS &R) {
699618
return BinaryOpc_match<LHS, RHS, true>(ISD::SMAX, L, R);
700619
}
701620

702-
template <typename LHS, typename RHS>
703-
inline auto m_SMaxLike(const LHS &L, const RHS &R) {
704-
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::SMAX, L, R),
705-
MaxMin_match<LHS, RHS, smax_pred_ty, true>(L, R));
706-
}
707-
708621
template <typename LHS, typename RHS>
709622
inline BinaryOpc_match<LHS, RHS, true> m_UMin(const LHS &L, const RHS &R) {
710623
return BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R);
711624
}
712625

713-
template <typename LHS, typename RHS>
714-
inline auto m_UMinLike(const LHS &L, const RHS &R) {
715-
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMIN, L, R),
716-
MaxMin_match<LHS, RHS, umin_pred_ty, true>(L, R));
717-
}
718-
719626
template <typename LHS, typename RHS>
720627
inline BinaryOpc_match<LHS, RHS, true> m_UMax(const LHS &L, const RHS &R) {
721628
return BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R);
722629
}
723630

724-
template <typename LHS, typename RHS>
725-
inline auto m_UMaxLike(const LHS &L, const RHS &R) {
726-
return m_AnyOf(BinaryOpc_match<LHS, RHS, true>(ISD::UMAX, L, R),
727-
MaxMin_match<LHS, RHS, umax_pred_ty, true>(L, R));
728-
}
729-
730631
template <typename LHS, typename RHS>
731632
inline BinaryOpc_match<LHS, RHS> m_UDiv(const LHS &L, const RHS &R) {
732633
return BinaryOpc_match<LHS, RHS>(ISD::UDIV, L, R);

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4190,26 +4190,26 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
41904190

41914191
// smax(a,b) - smin(a,b) --> abds(a,b)
41924192
if ((!LegalOperations || hasOperation(ISD::ABDS, VT)) &&
4193-
sd_match(N0, m_SMaxLike(m_Value(A), m_Value(B))) &&
4194-
sd_match(N1, m_SMinLike(m_Specific(A), m_Specific(B))))
4193+
sd_match(N0, m_SMax(m_Value(A), m_Value(B))) &&
4194+
sd_match(N1, m_SMin(m_Specific(A), m_Specific(B))))
41954195
return DAG.getNode(ISD::ABDS, DL, VT, A, B);
41964196

41974197
// smin(a,b) - smax(a,b) --> neg(abds(a,b))
41984198
if (hasOperation(ISD::ABDS, VT) &&
4199-
sd_match(N0, m_SMinLike(m_Value(A), m_Value(B))) &&
4200-
sd_match(N1, m_SMaxLike(m_Specific(A), m_Specific(B))))
4199+
sd_match(N0, m_SMin(m_Value(A), m_Value(B))) &&
4200+
sd_match(N1, m_SMax(m_Specific(A), m_Specific(B))))
42014201
return DAG.getNegative(DAG.getNode(ISD::ABDS, DL, VT, A, B), DL, VT);
42024202

42034203
// umax(a,b) - umin(a,b) --> abdu(a,b)
42044204
if ((!LegalOperations || hasOperation(ISD::ABDU, VT)) &&
4205-
sd_match(N0, m_UMaxLike(m_Value(A), m_Value(B))) &&
4206-
sd_match(N1, m_UMinLike(m_Specific(A), m_Specific(B))))
4205+
sd_match(N0, m_UMax(m_Value(A), m_Value(B))) &&
4206+
sd_match(N1, m_UMin(m_Specific(A), m_Specific(B))))
42074207
return DAG.getNode(ISD::ABDU, DL, VT, A, B);
42084208

42094209
// umin(a,b) - umax(a,b) --> neg(abdu(a,b))
42104210
if (hasOperation(ISD::ABDU, VT) &&
4211-
sd_match(N0, m_UMinLike(m_Value(A), m_Value(B))) &&
4212-
sd_match(N1, m_UMaxLike(m_Specific(A), m_Specific(B))))
4211+
sd_match(N0, m_UMin(m_Value(A), m_Value(B))) &&
4212+
sd_match(N1, m_UMax(m_Specific(A), m_Specific(B))))
42134213
return DAG.getNegative(DAG.getNode(ISD::ABDU, DL, VT, A, B), DL, VT);
42144214

42154215
return SDValue();

‎llvm/test/CodeGen/AArch64/abds.ll

Lines changed: 24 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -547,9 +547,10 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
547547
; CHECK-LABEL: abd_select_i8:
548548
; CHECK: // %bb.0:
549549
; CHECK-NEXT: sxtb w8, w0
550-
; CHECK-NEXT: sub w8, w8, w1, sxtb
551-
; CHECK-NEXT: cmp w8, #0
552-
; CHECK-NEXT: cneg w0, w8, mi
550+
; CHECK-NEXT: cmp w8, w1, sxtb
551+
; CHECK-NEXT: csel w8, w0, w1, lt
552+
; CHECK-NEXT: csel w9, w1, w0, lt
553+
; CHECK-NEXT: sub w0, w9, w8
553554
; CHECK-NEXT: ret
554555
%cmp = icmp slt i8 %a, %b
555556
%ab = select i1 %cmp, i8 %a, i8 %b
@@ -562,9 +563,10 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
562563
; CHECK-LABEL: abd_select_i16:
563564
; CHECK: // %bb.0:
564565
; CHECK-NEXT: sxth w8, w0
565-
; CHECK-NEXT: sub w8, w8, w1, sxth
566-
; CHECK-NEXT: cmp w8, #0
567-
; CHECK-NEXT: cneg w0, w8, mi
566+
; CHECK-NEXT: cmp w8, w1, sxth
567+
; CHECK-NEXT: csel w8, w0, w1, le
568+
; CHECK-NEXT: csel w9, w1, w0, le
569+
; CHECK-NEXT: sub w0, w9, w8
568570
; CHECK-NEXT: ret
569571
%cmp = icmp sle i16 %a, %b
570572
%ab = select i1 %cmp, i16 %a, i16 %b
@@ -576,9 +578,10 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
576578
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
577579
; CHECK-LABEL: abd_select_i32:
578580
; CHECK: // %bb.0:
579-
; CHECK-NEXT: sub w8, w1, w0
580-
; CHECK-NEXT: subs w9, w0, w1
581-
; CHECK-NEXT: csel w0, w9, w8, gt
581+
; CHECK-NEXT: cmp w0, w1
582+
; CHECK-NEXT: csel w8, w0, w1, gt
583+
; CHECK-NEXT: csel w9, w1, w0, gt
584+
; CHECK-NEXT: sub w0, w8, w9
582585
; CHECK-NEXT: ret
583586
%cmp = icmp sgt i32 %a, %b
584587
%ab = select i1 %cmp, i32 %a, i32 %b
@@ -590,9 +593,10 @@ define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
590593
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
591594
; CHECK-LABEL: abd_select_i64:
592595
; CHECK: // %bb.0:
593-
; CHECK-NEXT: sub x8, x1, x0
594-
; CHECK-NEXT: subs x9, x0, x1
595-
; CHECK-NEXT: csel x0, x9, x8, gt
596+
; CHECK-NEXT: cmp x0, x1
597+
; CHECK-NEXT: csel x8, x0, x1, ge
598+
; CHECK-NEXT: csel x9, x1, x0, ge
599+
; CHECK-NEXT: sub x0, x8, x9
596600
; CHECK-NEXT: ret
597601
%cmp = icmp sge i64 %a, %b
598602
%ab = select i1 %cmp, i64 %a, i64 %b
@@ -604,13 +608,14 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
604608
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
605609
; CHECK-LABEL: abd_select_i128:
606610
; CHECK: // %bb.0:
607-
; CHECK-NEXT: subs x8, x0, x2
608-
; CHECK-NEXT: sbc x9, x1, x3
609-
; CHECK-NEXT: subs x10, x2, x0
610-
; CHECK-NEXT: sbc x11, x3, x1
611-
; CHECK-NEXT: sbcs xzr, x3, x1
612-
; CHECK-NEXT: csel x0, x8, x10, lt
613-
; CHECK-NEXT: csel x1, x9, x11, lt
611+
; CHECK-NEXT: cmp x0, x2
612+
; CHECK-NEXT: sbcs xzr, x1, x3
613+
; CHECK-NEXT: csel x8, x0, x2, lt
614+
; CHECK-NEXT: csel x9, x2, x0, lt
615+
; CHECK-NEXT: csel x10, x1, x3, lt
616+
; CHECK-NEXT: csel x11, x3, x1, lt
617+
; CHECK-NEXT: subs x0, x9, x8
618+
; CHECK-NEXT: sbc x1, x11, x10
614619
; CHECK-NEXT: ret
615620
%cmp = icmp slt i128 %a, %b
616621
%ab = select i1 %cmp, i128 %a, i128 %b

‎llvm/test/CodeGen/AArch64/abdu.ll

Lines changed: 24 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -408,9 +408,10 @@ define i8 @abd_select_i8(i8 %a, i8 %b) nounwind {
408408
; CHECK-LABEL: abd_select_i8:
409409
; CHECK: // %bb.0:
410410
; CHECK-NEXT: and w8, w0, #0xff
411-
; CHECK-NEXT: sub w8, w8, w1, uxtb
412-
; CHECK-NEXT: cmp w8, #0
413-
; CHECK-NEXT: cneg w0, w8, mi
411+
; CHECK-NEXT: cmp w8, w1, uxtb
412+
; CHECK-NEXT: csel w8, w0, w1, lo
413+
; CHECK-NEXT: csel w9, w1, w0, lo
414+
; CHECK-NEXT: sub w0, w9, w8
414415
; CHECK-NEXT: ret
415416
%cmp = icmp ult i8 %a, %b
416417
%ab = select i1 %cmp, i8 %a, i8 %b
@@ -423,9 +424,10 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
423424
; CHECK-LABEL: abd_select_i16:
424425
; CHECK: // %bb.0:
425426
; CHECK-NEXT: and w8, w0, #0xffff
426-
; CHECK-NEXT: sub w8, w8, w1, uxth
427-
; CHECK-NEXT: cmp w8, #0
428-
; CHECK-NEXT: cneg w0, w8, mi
427+
; CHECK-NEXT: cmp w8, w1, uxth
428+
; CHECK-NEXT: csel w8, w0, w1, ls
429+
; CHECK-NEXT: csel w9, w1, w0, ls
430+
; CHECK-NEXT: sub w0, w9, w8
429431
; CHECK-NEXT: ret
430432
%cmp = icmp ule i16 %a, %b
431433
%ab = select i1 %cmp, i16 %a, i16 %b
@@ -437,9 +439,10 @@ define i16 @abd_select_i16(i16 %a, i16 %b) nounwind {
437439
define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
438440
; CHECK-LABEL: abd_select_i32:
439441
; CHECK: // %bb.0:
440-
; CHECK-NEXT: sub w8, w1, w0
441-
; CHECK-NEXT: subs w9, w0, w1
442-
; CHECK-NEXT: csel w0, w9, w8, hi
442+
; CHECK-NEXT: cmp w0, w1
443+
; CHECK-NEXT: csel w8, w0, w1, hi
444+
; CHECK-NEXT: csel w9, w1, w0, hi
445+
; CHECK-NEXT: sub w0, w8, w9
443446
; CHECK-NEXT: ret
444447
%cmp = icmp ugt i32 %a, %b
445448
%ab = select i1 %cmp, i32 %a, i32 %b
@@ -451,9 +454,10 @@ define i32 @abd_select_i32(i32 %a, i32 %b) nounwind {
451454
define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
452455
; CHECK-LABEL: abd_select_i64:
453456
; CHECK: // %bb.0:
454-
; CHECK-NEXT: sub x8, x1, x0
455-
; CHECK-NEXT: subs x9, x0, x1
456-
; CHECK-NEXT: csel x0, x9, x8, hi
457+
; CHECK-NEXT: cmp x0, x1
458+
; CHECK-NEXT: csel x8, x0, x1, hs
459+
; CHECK-NEXT: csel x9, x1, x0, hs
460+
; CHECK-NEXT: sub x0, x8, x9
457461
; CHECK-NEXT: ret
458462
%cmp = icmp uge i64 %a, %b
459463
%ab = select i1 %cmp, i64 %a, i64 %b
@@ -465,14 +469,14 @@ define i64 @abd_select_i64(i64 %a, i64 %b) nounwind {
465469
define i128 @abd_select_i128(i128 %a, i128 %b) nounwind {
466470
; CHECK-LABEL: abd_select_i128:
467471
; CHECK: // %bb.0:
468-
; CHECK-NEXT: subs x8, x0, x2
469-
; CHECK-NEXT: sbcs x9, x1, x3
470-
; CHECK-NEXT: cset w10, lo
471-
; CHECK-NEXT: sbfx x10, x10, #0, #1
472-
; CHECK-NEXT: eor x8, x8, x10
473-
; CHECK-NEXT: eor x9, x9, x10
474-
; CHECK-NEXT: subs x0, x8, x10
475-
; CHECK-NEXT: sbc x1, x9, x10
472+
; CHECK-NEXT: cmp x0, x2
473+
; CHECK-NEXT: sbcs xzr, x1, x3
474+
; CHECK-NEXT: csel x8, x0, x2, lo
475+
; CHECK-NEXT: csel x9, x2, x0, lo
476+
; CHECK-NEXT: csel x10, x1, x3, lo
477+
; CHECK-NEXT: csel x11, x3, x1, lo
478+
; CHECK-NEXT: subs x0, x9, x8
479+
; CHECK-NEXT: sbc x1, x11, x10
476480
; CHECK-NEXT: ret
477481
%cmp = icmp ult i128 %a, %b
478482
%ab = select i1 %cmp, i128 %a, i128 %b

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