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Merged main:5712e293fb31 into amd-gfx:5f712560902a
Local branch amd-gfx 5f71256 Merged main:8daba2c13dc3 into amd-gfx:2432d11e497d Remote branch main 5712e29 [CodeGen] Clean up tests that depend on implicit .text in MCAsmStreamer
2 parents 5f71256 + 5712e29 commit 0756140

21 files changed

+89
-65
lines changed

‎llvm/include/llvm/CodeGen/TargetRegisterInfo.h

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -347,13 +347,28 @@ class TargetRegisterInfo : public MCRegisterInfo {
347347
const TargetRegisterClass *getMinimalPhysRegClass(MCRegister Reg,
348348
MVT VT = MVT::Other) const;
349349

350+
/// Returns the common Register Class of two physical registers of the given
351+
/// type, picking the most sub register class of the right type that contains
352+
/// these two physregs.
353+
const TargetRegisterClass *
354+
getCommonMinimalPhysRegClass(MCRegister Reg1, MCRegister Reg2,
355+
MVT VT = MVT::Other) const;
356+
350357
/// Returns the Register Class of a physical register of the given type,
351358
/// picking the most sub register class of the right type that contains this
352359
/// physreg. If there is no register class compatible with the given type,
353360
/// returns nullptr.
354361
const TargetRegisterClass *getMinimalPhysRegClassLLT(MCRegister Reg,
355362
LLT Ty = LLT()) const;
356363

364+
/// Returns the common Register Class of two physical registers of the given
365+
/// type, picking the most sub register class of the right type that contains
366+
/// these two physregs. If there is no register class compatible with the
367+
/// given type, returns nullptr.
368+
const TargetRegisterClass *
369+
getCommonMinimalPhysRegClassLLT(MCRegister Reg1, MCRegister Reg2,
370+
LLT Ty = LLT()) const;
371+
357372
/// Return the maximal subclass of the given register class that is
358373
/// allocatable or NULL.
359374
const TargetRegisterClass *

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 522271
19+
#define LLVM_MAIN_REVISION 522275
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/CodeGen/TargetRegisterInfo.cpp

Lines changed: 59 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -201,44 +201,85 @@ TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
201201
return nullptr;
202202
}
203203

204-
/// getMinimalPhysRegClass - Returns the Register Class of a physical
205-
/// register of the given type, picking the most sub register class of
206-
/// the right type that contains this physreg.
207-
const TargetRegisterClass *
208-
TargetRegisterInfo::getMinimalPhysRegClass(MCRegister reg, MVT VT) const {
209-
assert(Register::isPhysicalRegister(reg) &&
204+
template <typename TypeT>
205+
static const TargetRegisterClass *
206+
getMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg,
207+
TypeT Ty) {
208+
static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
209+
assert(Register::isPhysicalRegister(Reg) &&
210210
"reg must be a physical register");
211211

212+
bool IsDefault = [&]() {
213+
if constexpr (std::is_same_v<TypeT, MVT>)
214+
return Ty == MVT::Other;
215+
else
216+
return !Ty.isValid();
217+
}();
218+
212219
// Pick the most sub register class of the right type that contains
213220
// this physreg.
214-
const TargetRegisterClass* BestRC = nullptr;
215-
for (const TargetRegisterClass* RC : regclasses()) {
216-
if ((VT == MVT::Other || isTypeLegalForClass(*RC, VT)) &&
217-
RC->contains(reg) && (!BestRC || BestRC->hasSubClass(RC)))
221+
const TargetRegisterClass *BestRC = nullptr;
222+
for (const TargetRegisterClass *RC : TRI->regclasses()) {
223+
if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) && RC->contains(Reg) &&
224+
(!BestRC || BestRC->hasSubClass(RC)))
218225
BestRC = RC;
219226
}
220227

221-
assert(BestRC && "Couldn't find the register class");
228+
if constexpr (std::is_same_v<TypeT, MVT>)
229+
assert(BestRC && "Couldn't find the register class");
222230
return BestRC;
223231
}
224232

225-
const TargetRegisterClass *
226-
TargetRegisterInfo::getMinimalPhysRegClassLLT(MCRegister reg, LLT Ty) const {
227-
assert(Register::isPhysicalRegister(reg) &&
228-
"reg must be a physical register");
233+
template <typename TypeT>
234+
static const TargetRegisterClass *
235+
getCommonMinimalPhysRegClass(const TargetRegisterInfo *TRI, MCRegister Reg1,
236+
MCRegister Reg2, TypeT Ty) {
237+
static_assert(std::is_same_v<TypeT, MVT> || std::is_same_v<TypeT, LLT>);
238+
assert(Register::isPhysicalRegister(Reg1) &&
239+
Register::isPhysicalRegister(Reg2) &&
240+
"Reg1/Reg2 must be a physical register");
241+
242+
bool IsDefault = [&]() {
243+
if constexpr (std::is_same_v<TypeT, MVT>)
244+
return Ty == MVT::Other;
245+
else
246+
return !Ty.isValid();
247+
}();
229248

230249
// Pick the most sub register class of the right type that contains
231250
// this physreg.
232251
const TargetRegisterClass *BestRC = nullptr;
233-
for (const TargetRegisterClass *RC : regclasses()) {
234-
if ((!Ty.isValid() || isTypeLegalForClass(*RC, Ty)) && RC->contains(reg) &&
235-
(!BestRC || BestRC->hasSubClass(RC)))
252+
for (const TargetRegisterClass *RC : TRI->regclasses()) {
253+
if ((IsDefault || TRI->isTypeLegalForClass(*RC, Ty)) &&
254+
RC->contains(Reg1, Reg2) && (!BestRC || BestRC->hasSubClass(RC)))
236255
BestRC = RC;
237256
}
238257

258+
if constexpr (std::is_same_v<TypeT, MVT>)
259+
assert(BestRC && "Couldn't find the register class");
239260
return BestRC;
240261
}
241262

263+
const TargetRegisterClass *
264+
TargetRegisterInfo::getMinimalPhysRegClass(MCRegister Reg, MVT VT) const {
265+
return ::getMinimalPhysRegClass(this, Reg, VT);
266+
}
267+
268+
const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClass(
269+
MCRegister Reg1, MCRegister Reg2, MVT VT) const {
270+
return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, VT);
271+
}
272+
273+
const TargetRegisterClass *
274+
TargetRegisterInfo::getMinimalPhysRegClassLLT(MCRegister Reg, LLT Ty) const {
275+
return ::getMinimalPhysRegClass(this, Reg, Ty);
276+
}
277+
278+
const TargetRegisterClass *TargetRegisterInfo::getCommonMinimalPhysRegClassLLT(
279+
MCRegister Reg1, MCRegister Reg2, LLT Ty) const {
280+
return ::getCommonMinimalPhysRegClass(this, Reg1, Reg2, Ty);
281+
}
282+
242283
/// getAllocatableSetForRC - Toggle the bits that represent allocatable
243284
/// registers for the specific register class.
244285
static void getAllocatableSetForRC(const MachineFunction &MF,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Lines changed: 6 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -390,7 +390,7 @@ void RISCVInstrInfo::copyPhysRegVector(
390390
auto FindRegWithEncoding = [TRI](const TargetRegisterClass &RegClass,
391391
uint16_t Encoding) {
392392
MCRegister Reg = RISCV::V0 + Encoding;
393-
if (&RegClass == &RISCV::VRRegClass)
393+
if (RISCVRI::getLMul(RegClass.TSFlags) == RISCVII::LMUL_1)
394394
return Reg;
395395
return TRI->getMatchingSuperReg(Reg, RISCV::sub_vrm1_0, &RegClass);
396396
};
@@ -564,17 +564,11 @@ void RISCVInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
564564
}
565565

566566
// VR->VR copies.
567-
static const TargetRegisterClass *RVVRegClasses[] = {
568-
&RISCV::VRRegClass, &RISCV::VRM2RegClass, &RISCV::VRM4RegClass,
569-
&RISCV::VRM8RegClass, &RISCV::VRN2M1RegClass, &RISCV::VRN2M2RegClass,
570-
&RISCV::VRN2M4RegClass, &RISCV::VRN3M1RegClass, &RISCV::VRN3M2RegClass,
571-
&RISCV::VRN4M1RegClass, &RISCV::VRN4M2RegClass, &RISCV::VRN5M1RegClass,
572-
&RISCV::VRN6M1RegClass, &RISCV::VRN7M1RegClass, &RISCV::VRN8M1RegClass};
573-
for (const auto &RegClass : RVVRegClasses) {
574-
if (RegClass->contains(DstReg, SrcReg)) {
575-
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
576-
return;
577-
}
567+
const TargetRegisterClass *RegClass =
568+
TRI->getCommonMinimalPhysRegClass(SrcReg, DstReg);
569+
if (RISCVRegisterInfo::isRVVRegClass(RegClass)) {
570+
copyPhysRegVector(MBB, MBBI, DL, DstReg, SrcReg, KillSrc, RegClass);
571+
return;
578572
}
579573

580574
llvm_unreachable("Impossible reg-to-reg copy");

‎llvm/test/CodeGen/AArch64/commandline-metadata.ll

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,14 @@
33

44
; Verify that llvm.commandline metadata is emitted to the corresponding command line section.
55

6-
; CHECK: .text
76
; CHECK: .section .GCC.command.line,"MS",@progbits,1
87
; CHECK-NEXT: .zero 1
98
; CHECK-NEXT: .ascii "clang -command1"
109
; CHECK-NEXT: .zero 1
1110
; CHECK-NEXT: .ascii "clang -command2"
1211
; CHECK-NEXT: .zero 1
1312

14-
; CHECK-MACHO: .section __TEXT,__text,regular,pure_instructions
15-
; CHECK-MACHO-NEXT: .section __TEXT,__command_line
13+
; CHECK-MACHO: .section __TEXT,__command_line
1614
; CHECK-MACHO-NEXT: .space 1
1715
; CHECK-MACHO-NEXT: .ascii "clang -command1"
1816
; CHECK-MACHO-NEXT: .space 1

‎llvm/test/CodeGen/AVR/sections.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,6 @@
99

1010
; Test that functions (in address space 1) are not considered .progmem data.
1111

12-
; CHECK: .text
1312
; SECTIONS: .text.somefunc,"ax",@progbits
1413
; CHECK-LABEL: somefunc:
1514
define void @somefunc() addrspace(1) {

‎llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@
55
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
66
target triple = "hexagon-unknown--elf"
77

8-
;FUNCTEXT: .text
98
;FUNCTEXT: .section{{.*}}tcm.hexagon,
109
;FUNCTEXT-NOT: .section{{.*}}.rodata
1110
;FUNCTEXT-NOT: .text

‎llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,6 @@
44
target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
55
target triple = "hexagon-unknown--elf"
66

7-
;FUNCTEXT: .text
87
;FUNCTEXT: .section{{.*}}text.foo,
98
;FUNCTEXT-NOT: .section{{.*}}.rodata
109
;FUNCTEXT: .Lswitch.table:

‎llvm/test/CodeGen/X86/GC/ocaml-gc.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,6 @@
11
; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
22

3-
; CHECK: .text
4-
; CHECK-NEXT: .file "<stdin>"
3+
; CHECK: .file "<stdin>"
54

65
define i32 @main(i32 %x) nounwind gc "ocaml" {
76
; CHECK: .globl "caml<stdin>__code_begin"

‎llvm/test/CodeGen/X86/basic-block-sections-blockaddress-taken.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,6 @@ entry:
66
%1 = select i1 %0, ptr blockaddress(@foo, %bb1), ptr blockaddress(@foo, %bb2) ; <ptr> [#uses=1]
77
indirectbr ptr %1, [label %bb1, label %bb2]
88

9-
; CHECK: .text
109
; CHECK: .section .text.foo,"ax",@progbits
1110
; CHECK-LABEL: foo:
1211
; CHECK: movl $.Ltmp0, %eax

‎llvm/test/CodeGen/X86/elf-unique-sections-by-flags.ll

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,10 +11,8 @@ define i32 @fn_text() {
1111
entry:
1212
ret i32 0
1313
}
14-
; CHECK: .text{{$}}
15-
; CHECK-NEXT: .file
1614
; FNSECTIONS: .section .text.fn_text,"ax",@progbits{{$}}
17-
; CHECK-NEXT: .globl fn_text
15+
; CHECK: .globl fn_text
1816
; CHECK: fn_text:
1917

2018
; A second function placed in .text, to check the behaviour with -function-sections.

‎llvm/test/CodeGen/Xtensa/simple.ll

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,6 @@
33

44
; CHECK: .text
55
; DUMP: file format elf32-xtensa
6+
define void @f() {
7+
ret void
8+
}

‎llvm/test/MC/AMDGPU/hsa-exp.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,6 @@
1313
// ELF: Section: .text
1414
// ELF: }
1515

16-
.text
17-
// ASM: .text
18-
1916
.amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
2017
// ASM: .amdgcn_target "amdgcn-unknown-amdhsa--gfx700"
2118

‎llvm/test/MC/AMDGPU/hsa-gfx12-v4.s

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -47,7 +47,6 @@
4747
// OBJDUMP-NEXT: 00f0 00000c60 80000000 00040000 00000000
4848

4949
.text
50-
// ASM: .text
5150

5251
.amdgcn_target "amdgcn-amd-amdhsa--gfx1200"
5352
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx1200"

‎llvm/test/MC/AMDGPU/hsa-tg-split.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,6 @@
88
// OBJDUMP-NEXT: 0020 00000000 00000000 00000000 00000100
99
// OBJDUMP-NEXT: 0030 0000ac00 80000000 00000000 00000000
1010

11-
.text
12-
// ASM: .text
13-
1411
.amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
1512
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
1613

‎llvm/test/MC/AMDGPU/hsa-v4.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -46,9 +46,6 @@
4646
// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000
4747
// OBJDUMP-NEXT: 00f0 0000ac00 80000000 00000000 00000000
4848

49-
.text
50-
// ASM: .text
51-
5249
.amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
5350
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
5451

‎llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -51,9 +51,6 @@
5151
// OBJDUMP-NEXT: 00e0 00000000 00000000 00000000 00000000
5252
// OBJDUMP-NEXT: 00f0 0000ac00 80000000 00000000 00000000
5353

54-
.text
55-
// ASM: .text
56-
5754
.amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
5855
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx904:xnack+"
5956

‎llvm/test/MC/AMDGPU/user-sgpr-count.s

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
11
// RUN: llvm-mc -triple amdgcn-amd-amdhsa -mcpu=gfx90a --amdhsa-code-object-version=4 -mattr=+xnack < %s | FileCheck --check-prefix=ASM %s
22

3-
.text
4-
// ASM: .text
5-
63
.amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
74
// ASM: .amdgcn_target "amdgcn-amd-amdhsa--gfx90a:xnack+"
85

‎llvm/test/MC/AsmParser/exprs-invalid.s

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
1-
// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err | FileCheck %s
1+
// RUN: not llvm-mc -triple x86_64-apple-darwin10 %s 2> %t.err
22
// RUN: FileCheck --check-prefix=CHECK-ERRORS %s < %t.err
3-
// CHECK: .section __TEXT,__text,regular,pure_instructions
43
// CHECK-ERRORS: :[[#@LINE+1]]:10: error: invalid octal number
54
.long 80+08
65

‎llvm/test/MC/GOFF/ppa1.ll

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@
2727
; CHECK: .short 0 * Length/4 of Parms
2828
; CHECK: .long L#func_end0-L#EPM_void_test_0 * Length of Code
2929
; CHECK: .long L#EPM_void_test_0-L#PPA1_void_test_0
30-
; CHECK: .section ".text"
3130
; CHECK: * -- End function
3231
define void @void_test() {
3332
entry:

‎llvm/test/MC/XCOFF/inlineasm.s

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,6 @@
11
// RUN: llvm-mc -filetype=asm -triple powerpc-ibm-aix-xcoff %s | FileCheck %s
22

3-
// CHECK-LABEL: .csect ..text..[PR],5
4-
// CHECK:L..tmp0:
5-
// CHECK-NEXT: lwarx 3, 0, 4
3+
// CHECK: lwarx 3, 0, 4
64
// CHECK-NEXT: cmpw 5, 3
75
// CHECK-NEXT: bne- 0, L..tmp1
86
// CHECK-NEXT: stwcx. 6, 0, 4

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