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Merged main:ad82d1c53f089937c05af11ff45798ceb5ca894e into amd-gfx:8662845fe7ba
Local branch amd-gfx 8662845 Merged main:626c7ce33f850831949e4e724016ddbff3a34990 into amd-gfx:1d2f2b3d50fe Remote branch main ad82d1c [clang][Interp][NFC] Move a lambda declaration into its closest scope
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‎clang/docs/ReleaseNotes.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -348,6 +348,9 @@ C23 Feature Support
348348
but C23 added them to ``<float.h>`` in
349349
`WG14 N2848 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2848.pdf>`_.
350350

351+
- Clang now supports `N3017 <https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3017.htm>`_
352+
``#embed`` - a scannable, tooling-friendly binary resource inclusion mechanism.
353+
351354
Non-comprehensive list of changes in this release
352355
-------------------------------------------------
353356

‎clang/lib/AST/Interp/Compiler.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3552,12 +3552,12 @@ VarCreationState Compiler<Emitter>::visitVarDecl(const VarDecl *VD, bool Topleve
35523552
const Expr *Init = VD->getInit();
35533553
std::optional<PrimType> VarT = classify(VD->getType());
35543554

3555-
auto checkDecl = [&]() -> bool {
3556-
bool NeedsOp = !Toplevel && VD->isLocalVarDecl() && VD->isStaticLocal();
3557-
return !NeedsOp || this->emitCheckDecl(VD, VD);
3558-
};
3559-
35603555
if (Context::shouldBeGloballyIndexed(VD)) {
3556+
auto checkDecl = [&]() -> bool {
3557+
bool NeedsOp = !Toplevel && VD->isLocalVarDecl() && VD->isStaticLocal();
3558+
return !NeedsOp || this->emitCheckDecl(VD, VD);
3559+
};
3560+
35613561
auto initGlobal = [&](unsigned GlobalIndex) -> bool {
35623562
assert(Init);
35633563
DeclScope<Emitter> LocalScope(this, VD);

‎clang/lib/AST/Interp/Disasm.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -325,8 +325,11 @@ LLVM_DUMP_METHOD void Record::dump(llvm::raw_ostream &OS, unsigned Indentation,
325325
LLVM_DUMP_METHOD void Block::dump(llvm::raw_ostream &OS) const {
326326
{
327327
ColorScope SC(OS, true, {llvm::raw_ostream::BRIGHT_BLUE, true});
328-
OS << "Block " << (const void *)this << "\n";
328+
OS << "Block " << (const void *)this;
329329
}
330+
OS << " (";
331+
Desc->dump(OS);
332+
OS << ")\n";
330333
unsigned NPointers = 0;
331334
for (const Pointer *P = Pointers; P; P = P->Next) {
332335
++NPointers;

‎clang/lib/AST/Interp/InterpBlock.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ DeadBlock::DeadBlock(DeadBlock *&Root, Block *Blk)
106106
B.Pointers = Blk->Pointers;
107107
for (Pointer *P = Blk->Pointers; P; P = P->Next)
108108
P->PointeeStorage.BS.Pointee = &B;
109+
Blk->Pointers = nullptr;
109110
}
110111

111112
void DeadBlock::free() {

‎clang/lib/AST/Interp/Pointer.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,9 @@ Pointer::~Pointer() {
5757
if (isIntegralPointer())
5858
return;
5959

60-
if (PointeeStorage.BS.Pointee) {
61-
PointeeStorage.BS.Pointee->removePointer(this);
62-
PointeeStorage.BS.Pointee->cleanup();
60+
if (Block *Pointee = PointeeStorage.BS.Pointee) {
61+
Pointee->removePointer(this);
62+
Pointee->cleanup();
6363
}
6464
}
6565

@@ -188,6 +188,7 @@ APValue Pointer::toAPValue() const {
188188
void Pointer::print(llvm::raw_ostream &OS) const {
189189
OS << PointeeStorage.BS.Pointee << " (";
190190
if (isBlockPointer()) {
191+
const Block *B = PointeeStorage.BS.Pointee;
191192
OS << "Block) {";
192193

193194
if (isRoot())
@@ -200,8 +201,8 @@ void Pointer::print(llvm::raw_ostream &OS) const {
200201
else
201202
OS << Offset << ", ";
202203

203-
if (PointeeStorage.BS.Pointee)
204-
OS << PointeeStorage.BS.Pointee->getSize();
204+
if (B)
205+
OS << B->getSize();
205206
else
206207
OS << "nullptr";
207208
} else {

‎clang/lib/Driver/Driver.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -681,7 +681,7 @@ static llvm::Triple computeTargetTriple(const Driver &D,
681681
if (Target.isRISCV()) {
682682
if (Args.hasArg(options::OPT_march_EQ) ||
683683
Args.hasArg(options::OPT_mcpu_EQ)) {
684-
StringRef ArchName = tools::riscv::getRISCVArch(Args, Target);
684+
std::string ArchName = tools::riscv::getRISCVArch(Args, Target);
685685
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
686686
ArchName, /*EnableExperimentalExtensions=*/true);
687687
if (!llvm::errorToBool(ISAInfo.takeError())) {

‎clang/lib/Driver/ToolChains/Arch/RISCV.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ static void getRISCFeaturesFromMcpu(const Driver &D, const Arg *A,
7272
void riscv::getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
7373
const ArgList &Args,
7474
std::vector<StringRef> &Features) {
75-
StringRef MArch = getRISCVArch(Args, Triple);
75+
std::string MArch = getRISCVArch(Args, Triple);
7676

7777
if (!getArchFeatures(D, MArch, Features, Args))
7878
return;
@@ -227,7 +227,7 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
227227
// rv64g | rv64*d -> lp64d
228228
// rv64e -> lp64e
229229
// rv64* -> lp64
230-
StringRef Arch = getRISCVArch(Args, Triple);
230+
std::string Arch = getRISCVArch(Args, Triple);
231231

232232
auto ParseResult = llvm::RISCVISAInfo::parseArchString(
233233
Arch, /* EnableExperimentalExtension */ true);
@@ -253,8 +253,8 @@ StringRef riscv::getRISCVABI(const ArgList &Args, const llvm::Triple &Triple) {
253253
}
254254
}
255255

256-
StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
257-
const llvm::Triple &Triple) {
256+
std::string riscv::getRISCVArch(const llvm::opt::ArgList &Args,
257+
const llvm::Triple &Triple) {
258258
assert(Triple.isRISCV() && "Unexpected triple");
259259

260260
// GCC's logic around choosing a default `-march=` is complex. If GCC is not
@@ -295,7 +295,7 @@ StringRef riscv::getRISCVArch(const llvm::opt::ArgList &Args,
295295
StringRef MArch = llvm::RISCV::getMArchFromMcpu(CPU);
296296
// Bypass if target cpu's default march is empty.
297297
if (MArch != "")
298-
return MArch;
298+
return MArch.str();
299299
}
300300

301301
// 3. Choose a default based on `-mabi=`

‎clang/lib/Driver/ToolChains/Arch/RISCV.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@ void getRISCVTargetFeatures(const Driver &D, const llvm::Triple &Triple,
2424
std::vector<llvm::StringRef> &Features);
2525
StringRef getRISCVABI(const llvm::opt::ArgList &Args,
2626
const llvm::Triple &Triple);
27-
StringRef getRISCVArch(const llvm::opt::ArgList &Args,
28-
const llvm::Triple &Triple);
27+
std::string getRISCVArch(const llvm::opt::ArgList &Args,
28+
const llvm::Triple &Triple);
2929
std::string getRISCVTargetCPU(const llvm::opt::ArgList &Args,
3030
const llvm::Triple &Triple);
3131
} // end namespace riscv

‎clang/lib/Driver/ToolChains/BareMetal.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@ static bool findRISCVMultilibs(const Driver &D,
3737
const llvm::Triple &TargetTriple,
3838
const ArgList &Args, DetectedMultilibs &Result) {
3939
Multilib::flags_list Flags;
40-
StringRef Arch = riscv::getRISCVArch(Args, TargetTriple);
40+
std::string Arch = riscv::getRISCVArch(Args, TargetTriple);
4141
StringRef Abi = tools::riscv::getRISCVABI(Args, TargetTriple);
4242

4343
if (TargetTriple.isRISCV64()) {

‎clang/lib/Driver/ToolChains/Clang.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2107,7 +2107,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args,
21072107

21082108
// Get minimum VLen from march.
21092109
unsigned MinVLen = 0;
2110-
StringRef Arch = riscv::getRISCVArch(Args, Triple);
2110+
std::string Arch = riscv::getRISCVArch(Args, Triple);
21112111
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
21122112
Arch, /*EnableExperimentalExtensions*/ true);
21132113
// Ignore parsing error.

‎clang/lib/Driver/ToolChains/Flang.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -204,7 +204,7 @@ void Flang::AddRISCVTargetArgs(const ArgList &Args,
204204

205205
// Get minimum VLen from march.
206206
unsigned MinVLen = 0;
207-
StringRef Arch = riscv::getRISCVArch(Args, Triple);
207+
std::string Arch = riscv::getRISCVArch(Args, Triple);
208208
auto ISAInfo = llvm::RISCVISAInfo::parseArchString(
209209
Arch, /*EnableExperimentalExtensions*/ true);
210210
// Ignore parsing error.

‎clang/lib/Driver/ToolChains/Gnu.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -769,9 +769,10 @@ void tools::gnutools::Assembler::ConstructJob(Compilation &C,
769769
StringRef ABIName = riscv::getRISCVABI(Args, getToolChain().getTriple());
770770
CmdArgs.push_back("-mabi");
771771
CmdArgs.push_back(ABIName.data());
772-
StringRef MArchName = riscv::getRISCVArch(Args, getToolChain().getTriple());
772+
std::string MArchName =
773+
riscv::getRISCVArch(Args, getToolChain().getTriple());
773774
CmdArgs.push_back("-march");
774-
CmdArgs.push_back(MArchName.data());
775+
CmdArgs.push_back(Args.MakeArgString(MArchName));
775776
if (!Args.hasFlag(options::OPT_mrelax, options::OPT_mno_relax, true))
776777
Args.addOptOutFlag(CmdArgs, options::OPT_mrelax, options::OPT_mno_relax);
777778
break;
@@ -1882,7 +1883,7 @@ static void findRISCVBareMetalMultilibs(const Driver &D,
18821883
Multilib::flags_list Flags;
18831884
llvm::StringSet<> Added_ABIs;
18841885
StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
1885-
StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
1886+
std::string MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
18861887
for (auto Element : RISCVMultilibSet) {
18871888
addMultilibFlag(MArch == Element.march,
18881889
Twine("-march=", Element.march).str().c_str(), Flags);

‎clang/lib/Sema/SemaRISCV.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1391,8 +1391,7 @@ void SemaRISCV::checkRVVTypeSupport(QualType Ty, SourceLocation Loc, Decl *D,
13911391
!FeatureMap.lookup("zvfhmin"))
13921392
Diag(Loc, diag::err_riscv_type_requires_extension, D)
13931393
<< Ty << "zvfh or zvfhmin";
1394-
else if (Info.ElementType->isBFloat16Type() &&
1395-
!FeatureMap.lookup("experimental-zvfbfmin"))
1394+
else if (Info.ElementType->isBFloat16Type() && !FeatureMap.lookup("zvfbfmin"))
13961395
Diag(Loc, diag::err_riscv_type_requires_extension, D) << Ty << "zvfbfmin";
13971396
else if (Info.ElementType->isSpecificBuiltinType(BuiltinType::Float) &&
13981397
!FeatureMap.lookup("zve32f"))

‎clang/test/AST/Interp/lifetimes.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify %s
2-
// RUN: %clang_cc1 -verify=ref %s
1+
// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -verify=expected,both %s
2+
// RUN: %clang_cc1 -verify=ref,both %s
33

44
struct Foo {
55
int a;
@@ -16,9 +16,7 @@ constexpr int dead1() { // expected-error {{never produces a constant expression
1616
return F2->a; // expected-note 2{{read of variable whose lifetime has ended}} \
1717
// ref-note {{read of object outside its lifetime is not allowed in a constant expression}}
1818
}
19-
static_assert(dead1() == 1, ""); // expected-error {{not an integral constant expression}} \
20-
// expected-note {{in call to}} \
21-
// ref-error {{not an integral constant expression}} \
22-
// ref-note {{in call to}} \
19+
static_assert(dead1() == 1, ""); // both-error {{not an integral constant expression}} \
20+
// both-note {{in call to}}
2321

2422

‎clang/test/AST/Interp/records.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -495,7 +495,7 @@ namespace DeclRefs {
495495
static_assert(b.a.m == 100, "");
496496
static_assert(b.a.f == 100, "");
497497

498-
constexpr B b2;
498+
constexpr B b2{};
499499
static_assert(b2.a.m == 100, "");
500500
static_assert(b2.a.f == 100, "");
501501
static_assert(b2.a.f == 101, ""); // both-error {{failed}} \

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

‎clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
22
// REQUIRES: riscv-registered-target
33
// RUN: %clang_cc1 -triple riscv64 -target-feature +v \
4-
// RUN: -target-feature +experimental-zvfbfmin \
5-
// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \
4+
// RUN: -target-feature +zvfbfmin \
5+
// RUN: -target-feature +zvfbfwma -disable-O0-optnone \
66
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
77
// RUN: FileCheck --check-prefix=CHECK-RV64 %s
88

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