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Merged main:9cee94b81b14 into amd-gfx:fe664d7a82a6
Local branch amd-gfx fe664d7 Merged main:024718313b52 into amd-gfx:ff07c6f2ec34 Remote branch main 9cee94b [GlobalISel] Add identity fold for fadd -0.0 (llvm#73296)
2 parents fe664d7 + 9cee94b commit 1dfdb7d

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11 files changed

+242
-45
lines changed

11 files changed

+242
-45
lines changed

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 481698
19+
#define LLVM_MAIN_REVISION 481703
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -473,6 +473,13 @@ def right_identity_zero: GICombineRule<
473473
(apply (GIReplaceReg $dst, $lhs))
474474
>;
475475

476+
def right_identity_neg_zero_fp: GICombineRule<
477+
(defs root:$dst),
478+
(match (G_FADD $dst, $x, $y):$root,
479+
[{ return Helper.matchConstantFPOp(${y}, -0.0); }]),
480+
(apply (GIReplaceReg $dst, $x))
481+
>;
482+
476483
// Fold x op 1 -> x
477484
def right_identity_one_int: GICombineRule<
478485
(defs root:$dst),
@@ -1250,7 +1257,8 @@ def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
12501257
add_sub_reg, buildvector_identity_fold,
12511258
trunc_buildvector_fold,
12521259
trunc_lshr_buildvector_fold,
1253-
bitcast_bitcast_fold, fptrunc_fpext_fold]>;
1260+
bitcast_bitcast_fold, fptrunc_fpext_fold,
1261+
right_identity_neg_zero_fp]>;
12541262

12551263
def const_combines : GICombineGroup<[constant_fold_fp_ops, const_ptradd_to_i2p,
12561264
overlapping_and, mulo_by_2, mulo_by_0,

‎llvm/lib/Target/MSP430/MSP430InstrInfo.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -305,12 +305,13 @@ def POP16r : IForm16<0b0100, DstReg, SrcPostInc, 2,
305305
let rs = 1;
306306
}
307307

308-
let mayStore = 1 in
308+
let mayStore = 1 in {
309309
def PUSH8r : II8r<0b100, (outs), (ins GR8:$rs), "push.b\t$rs", []>;
310310
def PUSH16r : II16r<0b100, (outs), (ins GR16:$rs), "push\t$rs", []>;
311311
def PUSH16c : II16c<0b100, (outs), (ins cg16imm:$imm), "push\t$imm", []>;
312312
def PUSH16i : II16i<0b100, (outs), (ins i16imm:$imm), "push\t$imm", []>;
313313
}
314+
}
314315

315316
//===----------------------------------------------------------------------===//
316317
// Move Instructions

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -293,6 +293,20 @@ RISCVInstructionSelector::selectSHXADD_UWOp(MachineOperand &Root,
293293

294294
InstructionSelector::ComplexRendererFns
295295
RISCVInstructionSelector::selectAddrRegImm(MachineOperand &Root) const {
296+
MachineFunction &MF = *Root.getParent()->getParent()->getParent();
297+
MachineRegisterInfo &MRI = MF.getRegInfo();
298+
299+
if (!Root.isReg())
300+
return std::nullopt;
301+
302+
MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
303+
if (RootDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) {
304+
return {{
305+
[=](MachineInstrBuilder &MIB) { MIB.add(RootDef->getOperand(1)); },
306+
[=](MachineInstrBuilder &MIB) { MIB.addImm(0); },
307+
}};
308+
}
309+
296310
// TODO: Need to get the immediate from a G_PTR_ADD. Should this be done in
297311
// the combiner?
298312
return {{[=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -127,3 +127,83 @@ body: |
127127
%3:_(<4 x s16>) = G_ADD %1, %2
128128
$x0 = COPY %3
129129
...
130+
---
131+
name: fadd_by_zero
132+
tracksRegLiveness: true
133+
body: |
134+
bb.0:
135+
liveins: $d0
136+
; CHECK-LABEL: name: fadd_by_zero
137+
; CHECK: liveins: $d0
138+
; CHECK-NEXT: {{ $}}
139+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
140+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
141+
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[C]]
142+
; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
143+
%0:_(s64) = COPY $d0
144+
%1:_(s64) = G_FCONSTANT double 0.000000e+00
145+
%2:_(s64) = G_FADD %0, %1(s64)
146+
$d0 = COPY %2(s64)
147+
...
148+
---
149+
name: fadd_vector_by_zero
150+
alignment: 4
151+
tracksRegLiveness: true
152+
frameInfo:
153+
maxAlignment: 1
154+
machineFunctionInfo: {}
155+
body: |
156+
bb.0:
157+
liveins: $q0
158+
; CHECK-LABEL: name: fadd_vector_by_zero
159+
; CHECK: liveins: $q0
160+
; CHECK-NEXT: {{ $}}
161+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
162+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
163+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
164+
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[COPY]], [[BUILD_VECTOR]]
165+
; CHECK-NEXT: $q0 = COPY [[FADD]](<4 x s32>)
166+
%0:_(<4 x s32>) = COPY $q0
167+
%1:_(s32) = G_FCONSTANT float 0.0
168+
%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
169+
%3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
170+
$q0 = COPY %3(<4 x s32>)
171+
...
172+
173+
---
174+
name: fadd_by_neg_zero
175+
tracksRegLiveness: true
176+
body: |
177+
bb.0:
178+
liveins: $d0
179+
; CHECK-LABEL: name: fadd_by_neg_zero
180+
; CHECK: liveins: $d0
181+
; CHECK-NEXT: {{ $}}
182+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
183+
; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
184+
%0:_(s64) = COPY $d0
185+
%1:_(s64) = G_FCONSTANT double -0.000000e+00
186+
%2:_(s64) = G_FADD %0, %1(s64)
187+
$d0 = COPY %2(s64)
188+
...
189+
---
190+
name: fadd_vector_by_neg_zero
191+
alignment: 4
192+
tracksRegLiveness: true
193+
frameInfo:
194+
maxAlignment: 1
195+
machineFunctionInfo: {}
196+
body: |
197+
bb.0:
198+
liveins: $q0
199+
; CHECK-LABEL: name: fadd_vector_by_neg_zero
200+
; CHECK: liveins: $q0
201+
; CHECK-NEXT: {{ $}}
202+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
203+
; CHECK-NEXT: $q0 = COPY [[COPY]](<4 x s32>)
204+
%0:_(<4 x s32>) = COPY $q0
205+
%1:_(s32) = G_FCONSTANT float -0.0
206+
%2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
207+
%3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
208+
$q0 = COPY %3(<4 x s32>)
209+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,21 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
4+
5+
--- |
6+
define void @load_i8(ptr %addr) { ret void }
7+
define void @load_i16(ptr %addr) { ret void }
8+
define void @load_i32(ptr %addr) { ret void }
9+
define void @zextload_i8(ptr %addr) { ret void }
10+
define void @zextload_i16(ptr %addr) { ret void }
11+
define void @sextload_i8(ptr %addr) { ret void }
12+
define void @sextload_i16(ptr %addr) { ret void }
13+
define void @load_p0(ptr %addr) { ret void }
14+
define void @load_fi_i32() {
15+
%ptr0 = alloca i32
16+
ret void
17+
}
18+
...
419
---
520
name: load_i8
621
legalized: true
@@ -177,3 +192,24 @@ body: |
177192
PseudoRET implicit $x10
178193
179194
...
195+
---
196+
name: load_fi_i32
197+
legalized: true
198+
regBankSelected: true
199+
tracksRegLiveness: true
200+
201+
stack:
202+
- { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
203+
204+
body: |
205+
bb.0:
206+
; CHECK-LABEL: name: load_fi_i32
207+
; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 0 :: (load (s32))
208+
; CHECK-NEXT: $x10 = COPY [[LW]]
209+
; CHECK-NEXT: PseudoRET implicit $x10
210+
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
211+
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
212+
$x10 = COPY %1(s32)
213+
PseudoRET implicit $x10
214+
215+
...

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,31 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
22
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
33
# RUN: | FileCheck %s
4+
5+
--- |
6+
define void @load_i8_i64(ptr %addr) { ret void }
7+
define void @load_i16_i64(ptr %addr) { ret void }
8+
define void @load_i32_i64(ptr %addr) { ret void }
9+
define void @load_i64_i64(ptr %addr) { ret void }
10+
define void @load_p0(ptr %addr) { ret void }
11+
define void @zextload_i8_i64(ptr %addr) { ret void }
12+
define void @zextload_i16_i64(ptr %addr) { ret void }
13+
define void @zextload_i32_i64(ptr %addr) { ret void }
14+
define void @sextload_i8_i64(ptr %addr) { ret void }
15+
define void @sextload_i16_i64(ptr %addr) { ret void }
16+
define void @sextload_i32_i64(ptr %addr) { ret void }
17+
define void @load_i8_i32(ptr %addr) { ret void }
18+
define void @load_i16_i32(ptr %addr) { ret void }
19+
define void @load_i32_i32(ptr %addr) { ret void }
20+
define void @zextload_i8_i32(ptr %addr) { ret void }
21+
define void @zextload_i16_i32(ptr %addr) { ret void }
22+
define void @sextload_i8_i32(ptr %addr) { ret void }
23+
define void @sextload_i16_i32(ptr %addr) { ret void }
24+
define void @load_fi_i64() {
25+
%ptr0 = alloca i64
26+
ret void
27+
}
28+
...
429
---
530
name: load_i8_i64
631
legalized: true
@@ -378,3 +403,78 @@ body: |
378403
PseudoRET implicit $x10
379404
380405
...
406+
---
407+
name: sextload_i8_i32
408+
legalized: true
409+
regBankSelected: true
410+
tracksRegLiveness: true
411+
body: |
412+
bb.0:
413+
liveins: $x10, $x11
414+
; CHECK-LABEL: name: sextload_i8_i32
415+
; CHECK: liveins: $x10, $x11
416+
; CHECK-NEXT: {{ $}}
417+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
418+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
419+
; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
420+
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[LB]], [[COPY1]]
421+
; CHECK-NEXT: $x10 = COPY [[ADDW]]
422+
; CHECK-NEXT: PseudoRET implicit $x10
423+
%0:gprb(p0) = COPY $x10
424+
%2:gprb(s64) = COPY $x11
425+
%9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
426+
%7:gprb(s32) = G_TRUNC %2(s64)
427+
%8:gprb(s32) = G_ADD %9, %7
428+
%5:gprb(s64) = G_ANYEXT %8(s32)
429+
$x10 = COPY %5(s64)
430+
PseudoRET implicit $x10
431+
432+
...
433+
---
434+
name: sextload_i16_i32
435+
legalized: true
436+
regBankSelected: true
437+
tracksRegLiveness: true
438+
body: |
439+
bb.0:
440+
liveins: $x10, $x11
441+
; CHECK-LABEL: name: sextload_i16_i32
442+
; CHECK: liveins: $x10, $x11
443+
; CHECK-NEXT: {{ $}}
444+
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
445+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
446+
; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
447+
; CHECK-NEXT: [[ADDW:%[0-9]+]]:gpr = ADDW [[LH]], [[COPY1]]
448+
; CHECK-NEXT: $x10 = COPY [[ADDW]]
449+
; CHECK-NEXT: PseudoRET implicit $x10
450+
%0:gprb(p0) = COPY $x10
451+
%2:gprb(s64) = COPY $x11
452+
%9:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
453+
%7:gprb(s32) = G_TRUNC %2(s64)
454+
%8:gprb(s32) = G_ADD %9, %7
455+
%5:gprb(s64) = G_ANYEXT %8(s32)
456+
$x10 = COPY %5(s64)
457+
PseudoRET implicit $x10
458+
459+
...
460+
---
461+
name: load_fi_i64
462+
legalized: true
463+
regBankSelected: true
464+
tracksRegLiveness: true
465+
466+
stack:
467+
- { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
468+
469+
body: |
470+
bb.0:
471+
; CHECK-LABEL: name: load_fi_i64
472+
; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 0 :: (load (s64))
473+
; CHECK-NEXT: $x10 = COPY [[LD]]
474+
; CHECK-NEXT: PseudoRET implicit $x10
475+
%0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
476+
%1:gprb(s64) = G_LOAD %0(p0) :: (load (s64))
477+
$x10 = COPY %1(s64)
478+
PseudoRET implicit $x10
479+
480+
...

‎mlir/include/mlir/Dialect/Arith/IR/ArithOps.td

Lines changed: 0 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -838,12 +838,6 @@ def Arith_SubFOp : Arith_FloatBinaryOp<"subf"> {
838838
def Arith_MaximumFOp : Arith_FloatBinaryOp<"maximumf", [Commutative]> {
839839
let summary = "floating-point maximum operation";
840840
let description = [{
841-
Syntax:
842-
843-
```
844-
operation ::= ssa-id `=` `arith.maximumf` ssa-use `,` ssa-use `:` type
845-
```
846-
847841
Returns the maximum of the two arguments, treating -0.0 as less than +0.0.
848842
If one of the arguments is NaN, then the result is also NaN.
849843

@@ -864,12 +858,6 @@ def Arith_MaximumFOp : Arith_FloatBinaryOp<"maximumf", [Commutative]> {
864858
def Arith_MaxNumFOp : Arith_FloatBinaryOp<"maxnumf", [Commutative]> {
865859
let summary = "floating-point maximum operation";
866860
let description = [{
867-
Syntax:
868-
869-
```
870-
operation ::= ssa-id `=` `arith.maxnumf` ssa-use `,` ssa-use `:` type
871-
```
872-
873861
Returns the maximum of the two arguments.
874862
If the arguments are -0.0 and +0.0, then the result is either of them.
875863
If one of the arguments is NaN, then the result is the other argument.
@@ -910,12 +898,6 @@ def Arith_MaxUIOp : Arith_TotalIntBinaryOp<"maxui", [Commutative]> {
910898
def Arith_MinimumFOp : Arith_FloatBinaryOp<"minimumf", [Commutative]> {
911899
let summary = "floating-point minimum operation";
912900
let description = [{
913-
Syntax:
914-
915-
```
916-
operation ::= ssa-id `=` `arith.minimumf` ssa-use `,` ssa-use `:` type
917-
```
918-
919901
Returns the minimum of the two arguments, treating -0.0 as less than +0.0.
920902
If one of the arguments is NaN, then the result is also NaN.
921903

@@ -936,12 +918,6 @@ def Arith_MinimumFOp : Arith_FloatBinaryOp<"minimumf", [Commutative]> {
936918
def Arith_MinNumFOp : Arith_FloatBinaryOp<"minnumf", [Commutative]> {
937919
let summary = "floating-point minimum operation";
938920
let description = [{
939-
Syntax:
940-
941-
```
942-
operation ::= ssa-id `=` `arith.minnumf` ssa-use `,` ssa-use `:` type
943-
```
944-
945921
Returns the minimum of the two arguments.
946922
If the arguments are -0.0 and +0.0, then the result is either of them.
947923
If one of the arguments is NaN, then the result is the other argument.

‎mlir/include/mlir/Dialect/Complex/IR/ComplexOps.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -280,12 +280,6 @@ def ExpOp : ComplexUnaryOp<"exp", [SameOperandsAndResultType]> {
280280
def Expm1Op : ComplexUnaryOp<"expm1", [SameOperandsAndResultType]> {
281281
let summary = "computes exponential of a complex number minus 1";
282282
let description = [{
283-
Syntax:
284-
285-
```
286-
operation ::= ssa-id `=` `complex.expm1` ssa-use `:` type
287-
```
288-
289283
complex.expm1(x) := complex.exp(x) - 1
290284

291285
Example:

‎mlir/include/mlir/Dialect/MemRef/IR/MemRefOps.td

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -447,12 +447,6 @@ def MemRef_CastOp : MemRef_Op<"cast", [
447447
]> {
448448
let summary = "memref cast operation";
449449
let description = [{
450-
Syntax:
451-
452-
```
453-
operation ::= ssa-id `=` `memref.cast` ssa-use `:` type `to` type
454-
```
455-
456450
The `memref.cast` operation converts a memref from one type to an equivalent
457451
type with a compatible shape. The source and destination types are
458452
compatible if:

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