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Merged main:84a20989c6f7 into amd-gfx:c2653d726cd0
Local branch amd-gfx c2653d7 Merged main:2170252b443f into amd-gfx:1dfdb7d72d2b Remote branch main 84a2098 [lld][LoongArch] Add a another corner testcase for elf::getLoongArchPageDelta
2 parents c2653d7 + 84a2098 commit 294af03

16 files changed

+711
-607
lines changed

‎lld/ELF/Arch/LoongArch.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -165,7 +165,6 @@ uint64_t elf::getLoongArchPageDelta(uint64_t dest, uint64_t pc) {
165165
result -= 0x10000'0000;
166166
else if (!negativeA && negativeB)
167167
result += 0x10000'0000;
168-
169168
return result;
170169
}
171170

‎lld/test/ELF/loongarch-pc-aligned.s

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -273,6 +273,19 @@
273273
# EXTREME16-NEXT: lu32i.d $t0, 0
274274
# EXTREME16-NEXT: lu52i.d $t0, $t0, 0
275275

276+
## FIXME: Correct %pc64_lo20 should be 0x00000 (0) and %pc64_hi12 should be 0x000 (0), but current values are:
277+
## page delta = 0xffffffff80000000, page offset = 0x888
278+
## %pc_lo12 = 0x888 = -1912
279+
## %pc_hi20 = 0x80000 = -524288
280+
## %pc64_lo20 = 0xfffff = -1
281+
## %pc64_hi12 = 0xfff = -1
282+
# RUN: ld.lld %t/extreme.o --section-start=.rodata=0x000071238ffff888 --section-start=.text=0x0000712310000678 -o %t/extreme17
283+
# RUN: llvm-objdump -d --no-show-raw-insn %t/extreme17 | FileCheck %s --check-prefix=EXTREME17
284+
# EXTREME17: addi.d $t0, $zero, -1912
285+
# EXTREME17-NEXT: pcalau12i $t1, -524288
286+
# EXTREME17-NEXT: lu32i.d $t0, -1
287+
# EXTREME17-NEXT: lu52i.d $t0, $t0, -1
288+
276289
#--- a.s
277290
.rodata
278291
x:

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 481704
19+
#define LLVM_MAIN_REVISION 481709
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/ExecutionEngine/JITLink/aarch32.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -388,7 +388,7 @@ void writeImmediate(WritableArmRelocation &R, uint32_t Imm) {
388388

389389
Expected<int64_t> readAddendData(LinkGraph &G, Block &B, Edge::OffsetT Offset,
390390
Edge::Kind Kind) {
391-
llvm::endianness Endian = G.getEndianness();
391+
endianness Endian = G.getEndianness();
392392
const char *BlockWorkingMem = B.getContent().data();
393393
const char *FixupPtr = BlockWorkingMem + Offset;
394394

@@ -467,10 +467,10 @@ Error applyFixupData(LinkGraph &G, Block &B, const Edge &E) {
467467
auto Write32 = [FixupPtr, Endian = G.getEndianness()](int64_t Value) {
468468
assert(isInt<32>(Value) && "Must be in signed 32-bit range");
469469
uint32_t Imm = static_cast<int32_t>(Value);
470-
if (LLVM_LIKELY(Endian == llvm::endianness::little))
471-
endian::write32<llvm::endianness::little>(FixupPtr, Imm);
470+
if (LLVM_LIKELY(Endian == endianness::little))
471+
endian::write32<endianness::little>(FixupPtr, Imm);
472472
else
473-
endian::write32<llvm::endianness::big>(FixupPtr, Imm);
473+
endian::write32<endianness::big>(FixupPtr, Imm);
474474
};
475475

476476
Edge::Kind Kind = E.getKind();

‎llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -74,10 +74,11 @@ const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
7474
// ARMFixupKinds.h.
7575
//
7676
// Name Offset (bits) Size (bits) Flags
77-
{"fixup_arm_ldst_pcrel_12", 0, 32, IsPCRelConstant},
77+
{"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
7878
{"fixup_t2_ldst_pcrel_12", 0, 32,
79-
IsPCRelConstant | MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
80-
{"fixup_arm_pcrel_10_unscaled", 0, 32, IsPCRelConstant},
79+
MCFixupKindInfo::FKF_IsPCRel |
80+
MCFixupKindInfo::FKF_IsAlignedDownTo32Bits},
81+
{"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
8182
{"fixup_arm_pcrel_10", 0, 32, IsPCRelConstant},
8283
{"fixup_t2_pcrel_10", 0, 32,
8384
MCFixupKindInfo::FKF_IsPCRel |

‎llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -158,6 +158,12 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target,
158158
default:
159159
return ELF::R_ARM_THM_CALL;
160160
}
161+
case ARM::fixup_arm_ldst_pcrel_12:
162+
return ELF::R_ARM_LDR_PC_G0;
163+
case ARM::fixup_arm_pcrel_10_unscaled:
164+
return ELF::R_ARM_LDRS_PC_G0;
165+
case ARM::fixup_t2_ldst_pcrel_12:
166+
return ELF::R_ARM_THM_PC12;
161167
case ARM::fixup_bf_target:
162168
return ELF::R_ARM_THM_BF16;
163169
case ARM::fixup_bfc_target:

‎llvm/test/MC/ARM/pcrel-arm-ldr-imm8-relocs.s

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
@ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
2+
@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=ARM
3+
@ RUN: llvm-objdump -d --triple=armv7 %t | FileCheck %s --check-prefix=ARM_ADDEND
4+
5+
@ ARM: R_ARM_LDRS_PC_G0
6+
@ ARM: R_ARM_LDRS_PC_G0
7+
@ ARM: R_ARM_LDRS_PC_G0
8+
@ ARM: R_ARM_LDRS_PC_G0
9+
@ ARM: R_ARM_LDRS_PC_G0
10+
@ ARM: R_ARM_LDRS_PC_G0
11+
12+
// The value format is decimal in these specific cases, but it's hex for other
13+
// ldr instructions. These checks are valid for both formats.
14+
15+
@ ARM_ADDEND: r0, [pc, #-{{(0x)?}}8]
16+
@ ARM_ADDEND: r0, [pc, #-{{(0x)?}}8]
17+
@ ARM_ADDEND: r0, [pc, #-{{(0x)?}}8]
18+
@ ARM_ADDEND: r0, [pc, #-{{16|0x10}}]
19+
@ ARM_ADDEND: r0, [pc, #-{{16|0x10}}]
20+
@ ARM_ADDEND: r0, [pc]
21+
22+
.arm
23+
.section .text.bar, "ax"
24+
.balign 4
25+
.global bar
26+
.type bar, %function
27+
bar:
28+
ldrh r0, foo
29+
ldrsb r0, foo
30+
ldrsh r0, foo
31+
ldrh r0, just_after-8
32+
ldrsb r0, just_after-8
33+
ldrsh r0, foo+8
34+
bx lr
35+
36+
.section .data.foo, "a", %progbits
37+
.balign 4
38+
.global foo
39+
foo:
40+
.word 0x11223344, 0x55667788
41+
just_after:
42+
.word 0x9900aabb, 0xccddeeff

‎llvm/test/MC/ARM/pcrel-global.s

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -9,21 +9,18 @@
99
@ DISASM-LABEL: <bar>:
1010
@ DISASM-NEXT: adr.w r0, #-4
1111
@ DISASM-NEXT: adr.w r0, #-8
12-
@ DISASM-NEXT: ldr.w pc, [pc, #-0xc] @ 0x10 <bar>
13-
@ DISASM-NEXT: ldr r0, [pc, #0x0] @ 0x20 <bar+0x10>
12+
@ DISASM-NEXT: ldr r0, [pc, #0x0] @ 0x14 <bar+0xc>
1413
@ DISASM-NEXT: add r0, pc
15-
@ DISASM-NEXT: .word 0xffffffef
14+
@ DISASM-NEXT: .word 0xfffffff3
1615
@@ GNU assembler creates an R_ARM_REL32 referencing bar.
1716
@ DISASM-NOT: {{.}}
1817

1918
.syntax unified
2019

2120
.globl foo
2221
foo:
23-
ldrd r0, r1, foo @ arm_pcrel_10_unscaled
2422
vldr d0, foo @ arm_pcrel_10
2523
adr r2, foo @ arm_adr_pcrel_12
26-
ldr r0, foo @ arm_ldst_pcrel_12
2724

2825
.thumb
2926
.thumb_func
@@ -32,7 +29,6 @@ ldr r0, foo @ arm_ldst_pcrel_12
3229
bar:
3330
adr r0, bar @ thumb_adr_pcrel_10
3431
adr.w r0, bar @ t2_adr_pcrel_12
35-
ldr.w pc, bar @ t2_ldst_pcrel_12
3632

3733
ldr r0, .LCPI
3834
.LPC0_1:

‎llvm/test/MC/ARM/pcrel-ldr-relocs.s

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,46 @@
1+
@ RUN: llvm-mc -filetype=obj -triple=armv7 %s -o %t
2+
@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=ARM
3+
@ RUN: llvm-objdump -d --triple=armv7 %t | FileCheck %s --check-prefix=ARM_ADDEND
4+
@ RUN: llvm-mc -filetype=obj -triple=thumbv7 %s -o %t
5+
@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB
6+
@ RUN: llvm-objdump -d --triple=thumbv7 %t | FileCheck %s --check-prefix=THUMB_ADDEND
7+
8+
@ ARM: R_ARM_LDR_PC_G0
9+
@ ARM: R_ARM_LDR_PC_G0
10+
@ ARM: R_ARM_LDR_PC_G0
11+
@ ARM: R_ARM_LDR_PC_G0
12+
13+
@ ARM_ADDEND: r0, [pc, #-0x8]
14+
@ ARM_ADDEND: r0, [pc, #-0x8]
15+
@ ARM_ADDEND: r0, [pc, #-0x10]
16+
@ ARM_ADDEND: r0, [pc]
17+
18+
@ THUMB: R_ARM_THM_PC12
19+
@ THUMB: R_ARM_THM_PC12
20+
@ THUMB: R_ARM_THM_PC12
21+
@ THUMB: R_ARM_THM_PC12
22+
23+
@ THUMB_ADDEND: r0, [pc, #-0x4]
24+
@ THUMB_ADDEND: r0, [pc, #-0x4]
25+
@ THUMB_ADDEND: r0, [pc, #-0xc]
26+
@ THUMB_ADDEND: r0, [pc, #0x4]
27+
28+
.section .text.bar, "ax"
29+
.balign 4
30+
.global bar
31+
.type bar, %function
32+
bar:
33+
ldr r0, foo1
34+
ldrb r0, foo1
35+
ldr r0, foo2-8
36+
ldrb r0, foo1+8
37+
bx lr
38+
39+
.section .data.foo, "a", %progbits
40+
.balign 4
41+
.global foo1
42+
.global foo2
43+
foo1:
44+
.word 0x11223344, 0x55667788
45+
foo2:
46+
.word 0x99aabbcc, 0xddeeff00

‎llvm/test/MC/ARM/pcrel-thumb-ldr2-relocs.s

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
@ RUN: llvm-mc -filetype=obj -triple=thumbv7 %s -o %t
2+
@ RUN: llvm-readelf -r %t | FileCheck %s --check-prefix=THUMB
3+
@ RUN: llvm-objdump -d --triple=thumbv7 %t | FileCheck %s --check-prefix=THUMB_ADDEND
4+
5+
@ All the ldr variants produce a relocation
6+
@ THUMB: R_ARM_THM_PC12
7+
@ THUMB: R_ARM_THM_PC12
8+
@ THUMB: R_ARM_THM_PC12
9+
@ THUMB: R_ARM_THM_PC12
10+
@ THUMB: R_ARM_THM_PC12
11+
@ THUMB: R_ARM_THM_PC12
12+
13+
@ THUMB_ADDEND: r0, [pc, #-0x4]
14+
@ THUMB_ADDEND: r0, [pc, #-0x4]
15+
@ THUMB_ADDEND: r0, [pc, #-0x4]
16+
@ THUMB_ADDEND: r0, [pc, #0x4]
17+
@ THUMB_ADDEND: r0, [pc, #-0xc]
18+
@ THUMB_ADDEND: r0, [pc, #0x4]
19+
20+
.thumb
21+
.section .text.bar, "ax"
22+
.balign 4
23+
.global bar
24+
.type bar, %function
25+
bar:
26+
ldrh r0, foo1
27+
ldrsb r0, foo1
28+
ldrsh r0, foo1
29+
ldrh r0, foo1+8
30+
ldrsb r0, foo2-8
31+
ldrsh r0, foo1+8
32+
bx lr
33+
34+
.section .data.foo, "a", %progbits
35+
.balign 4
36+
.global foo1
37+
.global foo2
38+
foo1:
39+
.word 0x11223344, 0x55667788
40+
foo2:
41+
.word 0x9900aabb, 0xccddeeff

‎llvm/test/MC/ARM/thumb1-relax-ldrlit.s

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
11
@ RUN: not llvm-mc -triple thumbv6m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
22
@ RUN: not llvm-mc -triple thumbv7m-none-macho -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
3-
@ RUN: not llvm-mc -triple thumbv7m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s
43

54
.global func1
65
_func1:

‎llvm/unittests/ExecutionEngine/JITLink/AArch32ErrorTests.cpp

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -19,8 +19,8 @@ using namespace llvm::support::endian;
1919

2020
constexpr unsigned PointerSize = 4;
2121
auto G = std::make_unique<LinkGraph>("foo", Triple("armv7-linux-gnueabi"),
22-
PointerSize, llvm::endianness::little,
23-
getGenericEdgeKindName);
22+
PointerSize, endianness::little,
23+
aarch32::getEdgeKindName);
2424
auto &Sec =
2525
G->createSection("__data", orc::MemProt::Read | orc::MemProt::Write);
2626

@@ -52,9 +52,10 @@ TEST(AArch32_ELF, readAddendArmErrors) {
5252
"INVALID RELOCATION")));
5353

5454
for (Edge::Kind K = FirstArmRelocation; K < LastArmRelocation; K += 1) {
55-
EXPECT_THAT_EXPECTED(
56-
readAddend(*G, BArm, SymbolOffset, K, ArmCfg),
57-
FailedWithMessage(testing::StartsWith("Invalid opcode")));
55+
EXPECT_THAT_EXPECTED(readAddend(*G, BArm, SymbolOffset, K, ArmCfg),
56+
FailedWithMessage(testing::AllOf(
57+
testing::StartsWith("Invalid opcode"),
58+
testing::EndsWith(aarch32::getEdgeKindName(K)))));
5859
}
5960
}
6061

@@ -76,9 +77,10 @@ TEST(AArch32_ELF, readAddendThumbErrors) {
7677
ThumbAlignment, AlignmentOffset);
7778

7879
for (Edge::Kind K = FirstThumbRelocation; K < LastThumbRelocation; K += 1) {
79-
EXPECT_THAT_EXPECTED(
80-
readAddend(*G, BThumb, SymbolOffset, K, ArmCfg),
81-
FailedWithMessage(testing::StartsWith("Invalid opcode")));
80+
EXPECT_THAT_EXPECTED(readAddend(*G, BThumb, SymbolOffset, K, ArmCfg),
81+
FailedWithMessage(testing::AllOf(
82+
testing::StartsWith("Invalid opcode"),
83+
testing::EndsWith(aarch32::getEdgeKindName(K)))));
8284
}
8385
}
8486

@@ -108,7 +110,7 @@ TEST(AArch32_ELF, applyFixupArmErrors) {
108110
EXPECT_THAT_ERROR(applyFixup(*G, BArm, E, ArmCfg),
109111
FailedWithMessage(testing::AllOf(
110112
testing::StartsWith("Invalid opcode"),
111-
testing::EndsWith(G->getEdgeKindName(K)))));
113+
testing::EndsWith(aarch32::getEdgeKindName(K)))));
112114
}
113115
}
114116

@@ -149,6 +151,6 @@ TEST(AArch32_ELF, applyFixupThumbErrors) {
149151
EXPECT_THAT_ERROR(applyFixup(*G, BThumb, E, ArmCfg),
150152
FailedWithMessage(testing::AllOf(
151153
testing::StartsWith("Invalid opcode"),
152-
testing::EndsWith(G->getEdgeKindName(K)))));
154+
testing::EndsWith(aarch32::getEdgeKindName(K)))));
153155
}
154156
}

‎llvm/unittests/ExecutionEngine/JITLink/AArch32Tests.cpp

Lines changed: 9 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -133,11 +133,9 @@ TEST(AArch32_Relocations, Thumb_Call_J1J2) {
133133
constexpr HalfWords ImmMask = FixupInfo<Thumb_Call>::ImmMask;
134134

135135
static std::array<HalfWords, 3> MemPresets{
136-
makeHalfWords<llvm::endianness::little>(
137-
{0xff, 0xf7, 0xfe, 0xef}), // common
138-
makeHalfWords<llvm::endianness::little>(
139-
{0x00, 0x00, 0x00, 0x00}), // zeros
140-
makeHalfWords<llvm::endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
136+
makeHalfWords<endianness::little>({0xff, 0xf7, 0xfe, 0xef}), // common
137+
makeHalfWords<endianness::little>({0x00, 0x00, 0x00, 0x00}), // zeros
138+
makeHalfWords<endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
141139
};
142140

143141
auto EncodeDecode = [ImmMask](int64_t In, MutableHalfWords &Mem) {
@@ -171,11 +169,9 @@ TEST(AArch32_Relocations, Thumb_Call_Bare) {
171169
constexpr HalfWords ImmMask = FixupInfo<Thumb_Call>::ImmMask;
172170

173171
static std::array<HalfWords, 3> MemPresets{
174-
makeHalfWords<llvm::endianness::little>(
175-
{0xff, 0xf7, 0xfe, 0xef}), // common
176-
makeHalfWords<llvm::endianness::little>(
177-
{0x00, 0x00, 0x00, 0x00}), // zeros
178-
makeHalfWords<llvm::endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
172+
makeHalfWords<endianness::little>({0xff, 0xf7, 0xfe, 0xef}), // common
173+
makeHalfWords<endianness::little>({0x00, 0x00, 0x00, 0x00}), // zeros
174+
makeHalfWords<endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
179175
};
180176

181177
auto EncodeDecode = [ImmMask](int64_t In, MutableHalfWords &Mem) {
@@ -244,11 +240,9 @@ TEST(AArch32_Relocations, Thumb_MovtAbs) {
244240

245241
static std::array<uint8_t, 3> Registers{0, 5, 12};
246242
static std::array<HalfWords, 3> MemPresets{
247-
makeHalfWords<llvm::endianness::little>(
248-
{0xff, 0xf7, 0xfe, 0xef}), // common
249-
makeHalfWords<llvm::endianness::little>(
250-
{0x00, 0x00, 0x00, 0x00}), // zeros
251-
makeHalfWords<llvm::endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
243+
makeHalfWords<endianness::little>({0xff, 0xf7, 0xfe, 0xef}), // common
244+
makeHalfWords<endianness::little>({0x00, 0x00, 0x00, 0x00}), // zeros
245+
makeHalfWords<endianness::little>({0xff, 0xff, 0xff, 0xff}), // ones
252246
};
253247

254248
auto EncodeDecode = [ImmMask](uint32_t In, MutableHalfWords &Mem) {

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