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[RISCV] Use Float type instead of Half type for Fixed RVV vector type mangling (llvm#73091)
1 parent e99ee06 commit 2eb9c64

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2 files changed

+71
-16
lines changed

2 files changed

+71
-16
lines changed

‎clang/lib/AST/ItaniumMangle.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4029,7 +4029,7 @@ void CXXNameMangler::mangleRISCVFixedRVVVectorType(const VectorType *T) {
40294029
case BuiltinType::ULong:
40304030
TypeNameOS << "uint64";
40314031
break;
4032-
case BuiltinType::Half:
4032+
case BuiltinType::Float16:
40334033
TypeNameOS << "float16";
40344034
break;
40354035
case BuiltinType::Float:

‎clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp

Lines changed: 70 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,23 +1,23 @@
11
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
2-
// RUN: -target-feature +f -target-feature +d \
3-
// RUN: -target-feature +zve64d -mvscale-min=1 -mvscale-max=1 \
4-
// RUN: | FileCheck %s --check-prefix=CHECK-64
2+
// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
3+
// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=1 \
4+
// RUN: -mvscale-max=1 | FileCheck %s --check-prefix=CHECK-64
55
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
6-
// RUN: -target-feature +f -target-feature +d \
7-
// RUN: -target-feature +zve64d -mvscale-min=2 -mvscale-max=2 \
8-
// RUN: | FileCheck %s --check-prefix=CHECK-128
6+
// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
7+
// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=2 \
8+
// RUN: -mvscale-max=2 | FileCheck %s --check-prefix=CHECK-128
99
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
10-
// RUN: -target-feature +f -target-feature +d \
11-
// RUN: -target-feature +zve64d -mvscale-min=4 -mvscale-max=4 \
12-
// RUN: | FileCheck %s --check-prefix=CHECK-256
10+
// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
11+
// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=4 \
12+
// RUN: -mvscale-max=4 | FileCheck %s --check-prefix=CHECK-256
1313
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
14-
// RUN: -target-feature +f -target-feature +d \
15-
// RUN: -target-feature +zve64d -mvscale-min=8 -mvscale-max=8 \
16-
// RUN: | FileCheck %s --check-prefix=CHECK-512
14+
// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
15+
// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=8 \
16+
// RUN: -mvscale-max=8 | FileCheck %s --check-prefix=CHECK-512
1717
// RUN: %clang_cc1 -triple riscv64-none-linux-gnu %s -emit-llvm -o - \
18-
// RUN: -target-feature +f -target-feature +d \
19-
// RUN: -target-feature +zve64d -mvscale-min=16 -mvscale-max=16 \
20-
// RUN: | FileCheck %s --check-prefix=CHECK-1024
18+
// RUN: -target-feature +f -target-feature +d -target-feature +zfh \
19+
// RUN: -target-feature +zve64d -target-feature +zvfh -mvscale-min=16 \
20+
// RUN: -mvscale-max=16 | FileCheck %s --check-prefix=CHECK-1024
2121

2222
typedef __rvv_int8mf8_t vint8mf8_t;
2323
typedef __rvv_uint8mf8_t vuint8mf8_t;
@@ -26,13 +26,15 @@ typedef __rvv_int8mf4_t vint8mf4_t;
2626
typedef __rvv_uint8mf4_t vuint8mf4_t;
2727
typedef __rvv_int16mf4_t vint16mf4_t;
2828
typedef __rvv_uint16mf4_t vuint16mf4_t;
29+
typedef __rvv_float16mf4_t vfloat16mf4_t;
2930

3031
typedef __rvv_int8mf2_t vint8mf2_t;
3132
typedef __rvv_uint8mf2_t vuint8mf2_t;
3233
typedef __rvv_int16mf2_t vint16mf2_t;
3334
typedef __rvv_uint16mf2_t vuint16mf2_t;
3435
typedef __rvv_int32mf2_t vint32mf2_t;
3536
typedef __rvv_uint32mf2_t vuint32mf2_t;
37+
typedef __rvv_float16mf2_t vfloat16mf2_t;
3638
typedef __rvv_float32mf2_t vfloat32mf2_t;
3739

3840
typedef __rvv_int8m1_t vint8m1_t;
@@ -43,6 +45,7 @@ typedef __rvv_int32m1_t vint32m1_t;
4345
typedef __rvv_uint32m1_t vuint32m1_t;
4446
typedef __rvv_int64m1_t vint64m1_t;
4547
typedef __rvv_uint64m1_t vuint64m1_t;
48+
typedef __rvv_float16m1_t vfloat16m1_t;
4649
typedef __rvv_float32m1_t vfloat32m1_t;
4750
typedef __rvv_float64m1_t vfloat64m1_t;
4851

@@ -54,6 +57,7 @@ typedef __rvv_int32m2_t vint32m2_t;
5457
typedef __rvv_uint32m2_t vuint32m2_t;
5558
typedef __rvv_int64m2_t vint64m2_t;
5659
typedef __rvv_uint64m2_t vuint64m2_t;
60+
typedef __rvv_float16m2_t vfloat16m2_t;
5761
typedef __rvv_float32m2_t vfloat32m2_t;
5862
typedef __rvv_float64m2_t vfloat64m2_t;
5963

@@ -65,6 +69,7 @@ typedef __rvv_int32m4_t vint32m4_t;
6569
typedef __rvv_uint32m4_t vuint32m4_t;
6670
typedef __rvv_int64m4_t vint64m4_t;
6771
typedef __rvv_uint64m4_t vuint64m4_t;
72+
typedef __rvv_float16m4_t vfloat16m4_t;
6873
typedef __rvv_float32m4_t vfloat32m4_t;
6974
typedef __rvv_float64m4_t vfloat64m4_t;
7075

@@ -76,6 +81,7 @@ typedef __rvv_int32m8_t vint32m8_t;
7681
typedef __rvv_uint32m8_t vuint32m8_t;
7782
typedef __rvv_int64m8_t vint64m8_t;
7883
typedef __rvv_uint64m8_t vuint64m8_t;
84+
typedef __rvv_float16m8_t vfloat16m8_t;
7985
typedef __rvv_float32m8_t vfloat32m8_t;
8086
typedef __rvv_float64m8_t vfloat64m8_t;
8187

@@ -89,6 +95,8 @@ typedef vint16mf4_t fixed_int16mf4_t __attribute__((riscv_rvv_vector_bits(__risc
8995
typedef vuint8mf4_t fixed_uint8mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
9096
typedef vuint16mf4_t fixed_uint16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
9197

98+
typedef vfloat16mf4_t fixed_float16mf4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/4)));
99+
92100
typedef vint8mf2_t fixed_int8mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
93101
typedef vint16mf2_t fixed_int16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
94102
typedef vint32mf2_t fixed_int32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
@@ -97,6 +105,7 @@ typedef vuint8mf2_t fixed_uint8mf2_t __attribute__((riscv_rvv_vector_bits(__risc
97105
typedef vuint16mf2_t fixed_uint16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
98106
typedef vuint32mf2_t fixed_uint32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
99107

108+
typedef vfloat16mf2_t fixed_float16mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
100109
typedef vfloat32mf2_t fixed_float32mf2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen/2)));
101110

102111
typedef vint8m1_t fixed_int8m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
@@ -109,6 +118,7 @@ typedef vuint16m1_t fixed_uint16m1_t __attribute__((riscv_rvv_vector_bits(__risc
109118
typedef vuint32m1_t fixed_uint32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
110119
typedef vuint64m1_t fixed_uint64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
111120

121+
typedef vfloat16m1_t fixed_float16m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
112122
typedef vfloat32m1_t fixed_float32m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
113123
typedef vfloat64m1_t fixed_float64m1_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen)));
114124

@@ -122,6 +132,7 @@ typedef vuint16m2_t fixed_uint16m2_t __attribute__((riscv_rvv_vector_bits(__risc
122132
typedef vuint32m2_t fixed_uint32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
123133
typedef vuint64m2_t fixed_uint64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
124134

135+
typedef vfloat16m2_t fixed_float16m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
125136
typedef vfloat32m2_t fixed_float32m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
126137
typedef vfloat64m2_t fixed_float64m2_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*2)));
127138

@@ -135,6 +146,7 @@ typedef vuint16m4_t fixed_uint16m4_t __attribute__((riscv_rvv_vector_bits(__risc
135146
typedef vuint32m4_t fixed_uint32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
136147
typedef vuint64m4_t fixed_uint64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
137148

149+
typedef vfloat16m4_t fixed_float16m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
138150
typedef vfloat32m4_t fixed_float32m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
139151
typedef vfloat64m4_t fixed_float64m4_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*4)));
140152

@@ -148,6 +160,7 @@ typedef vuint16m8_t fixed_uint16m8_t __attribute__((riscv_rvv_vector_bits(__risc
148160
typedef vuint32m8_t fixed_uint32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
149161
typedef vuint64m8_t fixed_uint64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
150162

163+
typedef vfloat16m8_t fixed_float16m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
151164
typedef vfloat32m8_t fixed_float32m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
152165
typedef vfloat64m8_t fixed_float64m8_t __attribute__((riscv_rvv_vector_bits(__riscv_v_fixed_vlen*8)));
153166

@@ -223,6 +236,13 @@ void f9(S<fixed_float32m1_t>) {}
223236
// CHECK-1024: _Z3f101SI9__RVV_VLSIu17__rvv_float64m1_tLj1024EEE
224237
void f10(S<fixed_float64m1_t>) {}
225238

239+
// CHECK-64: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj64EEE
240+
// CHECK-128: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj128EEE
241+
// CHECK-256: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj256EEE
242+
// CHECK-512: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj512EEE
243+
// CHECK-1024: _Z3f111SI9__RVV_VLSIu17__rvv_float16m1_tLj1024EEE
244+
void f11(S<fixed_float16m1_t>) {}
245+
226246
// CHECK-64: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj128EEE
227247
// CHECK-128: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj256EEE
228248
// CHECK-256: _Z4m2f11SI9__RVV_VLSIu14__rvv_int8m2_tLj512EEE
@@ -293,6 +313,13 @@ void m2f9(S<fixed_float32m2_t>) {}
293313
// CHECK-1024: _Z5m2f101SI9__RVV_VLSIu17__rvv_float64m2_tLj2048EEE
294314
void m2f10(S<fixed_float64m2_t>) {}
295315

316+
// CHECK-64: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj128EEE
317+
// CHECK-128: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj256EEE
318+
// CHECK-256: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj512EEE
319+
// CHECK-512: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj1024EEE
320+
// CHECK-1024: _Z5m2f111SI9__RVV_VLSIu17__rvv_float16m2_tLj2048EEE
321+
void m2f11(S<fixed_float16m2_t>) {}
322+
296323
// CHECK-64: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj256EEE
297324
// CHECK-128: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj512EEE
298325
// CHECK-256: _Z4m4f11SI9__RVV_VLSIu14__rvv_int8m4_tLj1024EEE
@@ -363,6 +390,13 @@ void m4f9(S<fixed_float32m4_t>) {}
363390
// CHECK-1024: _Z5m4f101SI9__RVV_VLSIu17__rvv_float64m4_tLj4096EEE
364391
void m4f10(S<fixed_float64m4_t>) {}
365392

393+
// CHECK-64: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj256EEE
394+
// CHECK-128: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj512EEE
395+
// CHECK-256: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj1024EEE
396+
// CHECK-512: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj2048EEE
397+
// CHECK-1024: _Z5m4f111SI9__RVV_VLSIu17__rvv_float16m4_tLj4096EEE
398+
void m4f11(S<fixed_float16m4_t>) {}
399+
366400
// CHECK-64: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj512EEE
367401
// CHECK-128: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj1024EEE
368402
// CHECK-256: _Z4m8f11SI9__RVV_VLSIu14__rvv_int8m8_tLj2048EEE
@@ -433,6 +467,13 @@ void m8f9(S<fixed_float32m8_t>) {}
433467
// CHECK-1024: _Z5m8f101SI9__RVV_VLSIu17__rvv_float64m8_tLj8192EEE
434468
void m8f10(S<fixed_float64m8_t>) {}
435469

470+
// CHECK-64: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj512EEE
471+
// CHECK-128: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj1024EEE
472+
// CHECK-256: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj2048EEE
473+
// CHECK-512: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj4096EEE
474+
// CHECK-1024: _Z5m8f111SI9__RVV_VLSIu17__rvv_float16m8_tLj8192EEE
475+
void m8f11(S<fixed_float16m8_t>) {}
476+
436477
// CHECK-64: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj32EEE
437478
// CHECK-128: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj64EEE
438479
// CHECK-256: _Z5mf2f11SI9__RVV_VLSIu15__rvv_int8mf2_tLj128EEE
@@ -482,6 +523,13 @@ void mf2f7(S<fixed_uint32mf2_t>) {}
482523
// CHECK-1024: _Z5mf2f91SI9__RVV_VLSIu18__rvv_float32mf2_tLj512EEE
483524
void mf2f9(S<fixed_float32mf2_t>) {}
484525

526+
// CHECK-64: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj32EEE
527+
// CHECK-128: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj64EEE
528+
// CHECK-256: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj128EEE
529+
// CHECK-512: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj256EEE
530+
// CHECK-1024: _Z6mf2f101SI9__RVV_VLSIu18__rvv_float16mf2_tLj512EEE
531+
void mf2f10(S<fixed_float16mf2_t>) {}
532+
485533
// CHECK-64: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj16EEE
486534
// CHECK-128: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj32EEE
487535
// CHECK-256: _Z5mf4f11SI9__RVV_VLSIu15__rvv_int8mf4_tLj64EEE
@@ -510,6 +558,13 @@ void mf4f5(S<fixed_uint8mf4_t>) {}
510558
// CHECK-1024: _Z5mf4f61SI9__RVV_VLSIu17__rvv_uint16mf4_tLj256EEE
511559
void mf4f6(S<fixed_uint16mf4_t>) {}
512560

561+
// CHECK-64: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj16EEE
562+
// CHECK-128: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj32EEE
563+
// CHECK-256: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj64EEE
564+
// CHECK-512: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj128EEE
565+
// CHECK-1024: _Z5mf4f71SI9__RVV_VLSIu18__rvv_float16mf4_tLj256EEE
566+
void mf4f7(S<fixed_float16mf4_t>) {}
567+
513568
// CHECK-64: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj8EEE
514569
// CHECK-128: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj16EEE
515570
// CHECK-256: _Z5mf8f11SI9__RVV_VLSIu15__rvv_int8mf8_tLj32EEE

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