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Merged main:e0217ee7829cf49bc0caa8b814f6acc4c4b0836d into amd-gfx:1d6313d1092c
Local branch amd-gfx 1d6313d Merged main:9940620f6eab50deeaed0d976b2ea0afd007ba24 into amd-gfx:7a792ea49b6b Remote branch main e0217ee [DAG] canCreateUndefOrPoison - only compute extract/index vector elt index knownbits when not poison
2 parents 1d6313d + e0217ee commit 319b068

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6 files changed

+187
-11
lines changed

6 files changed

+187
-11
lines changed

‎compiler-rt/test/ctx_profile/TestCases/generate-context.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@
55
// RUN: cp %llvm_src/include/llvm/ProfileData/CtxInstrContextNode.h %t_include/
66
//
77
// Compile with ctx instrumentation "on". We treat "theRoot" as callgraph root.
8-
// RUN: %clangxx %s -lclang_rt.ctx_profile -I%t_include -O2 -o %t.bin -mllvm -profile-context-root=theRoot
8+
// RUN: %clangxx %s %ctxprofilelib -I%t_include -O2 -o %t.bin -mllvm -profile-context-root=theRoot
99
//
1010
// Run the binary, and observe the profile fetch handler's output.
1111
// RUN: %t.bin | FileCheck %s

‎compiler-rt/test/ctx_profile/lit.cfg.py

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -33,3 +33,10 @@ def get_required_attr(config, attr_name):
3333
config.substitutions.append(
3434
("%clangxx ", " ".join([config.clang] + config.cxx_mode_flags) + " -ldl -lpthread ")
3535
)
36+
37+
config.substitutions.append(
38+
(
39+
"%ctxprofilelib",
40+
"-L%s -lclang_rt.ctx_profile%s" % (config.compiler_rt_libdir, config.target_suffix)
41+
)
42+
)

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 499119
19+
#define LLVM_MAIN_REVISION 499123
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 8 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5241,18 +5241,17 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts,
52415241
// Check if we demand any upper (undef) elements.
52425242
return !PoisonOnly && DemandedElts.ugt(1);
52435243

5244+
case ISD::INSERT_VECTOR_ELT:
52445245
case ISD::EXTRACT_VECTOR_ELT: {
52455246
// Ensure that the element index is in bounds.
52465247
EVT VecVT = Op.getOperand(0).getValueType();
5247-
KnownBits KnownIdx = computeKnownBits(Op.getOperand(1), Depth + 1);
5248-
return KnownIdx.getMaxValue().uge(VecVT.getVectorMinNumElements());
5249-
}
5250-
5251-
case ISD::INSERT_VECTOR_ELT:{
5252-
// Ensure that the element index is in bounds.
5253-
EVT VecVT = Op.getOperand(0).getValueType();
5254-
KnownBits KnownIdx = computeKnownBits(Op.getOperand(2), Depth + 1);
5255-
return KnownIdx.getMaxValue().uge(VecVT.getVectorMinNumElements());
5248+
SDValue Idx = Op.getOperand(Opcode == ISD::INSERT_VECTOR_ELT ? 2 : 1);
5249+
if (isGuaranteedNotToBeUndefOrPoison(Idx, DemandedElts, PoisonOnly,
5250+
Depth + 1)) {
5251+
KnownBits KnownIdx = computeKnownBits(Idx, Depth + 1);
5252+
return KnownIdx.getMaxValue().uge(VecVT.getVectorMinNumElements());
5253+
}
5254+
return true;
52565255
}
52575256

52585257
case ISD::VECTOR_SHUFFLE: {

‎llvm/test/CodeGen/X86/pr92569.ll

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc < %s -mtriple=x86_64-linux-gnu | FileCheck %s
3+
4+
define void @PR92569(i64 %arg, <8 x i8> %arg1) {
5+
; CHECK-LABEL: PR92569:
6+
; CHECK: # %bb.0:
7+
; CHECK-NEXT: testq %rdi, %rdi
8+
; CHECK-NEXT: je .LBB0_1
9+
; CHECK-NEXT: # %bb.2: # %cond.false
10+
; CHECK-NEXT: rep bsfq %rdi, %rax
11+
; CHECK-NEXT: jmp .LBB0_3
12+
; CHECK-NEXT: .LBB0_1:
13+
; CHECK-NEXT: movl $64, %eax
14+
; CHECK-NEXT: .LBB0_3: # %cond.end
15+
; CHECK-NEXT: shrb $3, %al
16+
; CHECK-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
17+
; CHECK-NEXT: movzbl %al, %eax
18+
; CHECK-NEXT: movzbl -24(%rsp,%rax), %eax
19+
; CHECK-NEXT: movl %eax, 0
20+
; CHECK-NEXT: retq
21+
%cttz = call i64 @llvm.cttz.i64(i64 %arg, i1 false)
22+
%trunc = trunc i64 %cttz to i8
23+
%lshr = lshr i8 %trunc, 3
24+
%extractelement = extractelement <8 x i8> %arg1, i8 %lshr
25+
%freeze = freeze i8 %extractelement
26+
%zext = zext i8 %freeze to i32
27+
store i32 %zext, ptr addrspace(1) null, align 4
28+
ret void
29+
}

‎llvm/test/Transforms/VectorCombine/AArch64/shuffletoidentity.ll

Lines changed: 141 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -465,6 +465,125 @@ define void @exttrunc(<8 x i32> %a, <8 x i32> %b, ptr %p) {
465465
ret void
466466
}
467467

468+
define void @zext(<8 x i16> %a, <8 x i16> %b, ptr %p) {
469+
; CHECK-LABEL: @zext(
470+
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
471+
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
472+
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x i16> [[B:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
473+
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
474+
; CHECK-NEXT: [[AB1:%.*]] = zext <4 x i16> [[AB]] to <4 x i32>
475+
; CHECK-NEXT: [[AT1:%.*]] = zext <4 x i16> [[AT]] to <4 x i32>
476+
; CHECK-NEXT: [[BB1:%.*]] = zext <4 x i16> [[BB]] to <4 x i32>
477+
; CHECK-NEXT: [[BT1:%.*]] = zext <4 x i16> [[BT]] to <4 x i32>
478+
; CHECK-NEXT: [[ABB:%.*]] = add <4 x i32> [[AB1]], [[BB1]]
479+
; CHECK-NEXT: [[ABT:%.*]] = add <4 x i32> [[AT1]], [[BT1]]
480+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[ABB]], <4 x i32> [[ABT]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
481+
; CHECK-NEXT: store <8 x i32> [[R]], ptr [[P:%.*]], align 32
482+
; CHECK-NEXT: ret void
483+
;
484+
%ab = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
485+
%at = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
486+
%bb = shufflevector <8 x i16> %b, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
487+
%bt = shufflevector <8 x i16> %b, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
488+
%ab1 = zext <4 x i16> %ab to <4 x i32>
489+
%at1 = zext <4 x i16> %at to <4 x i32>
490+
%bb1 = zext <4 x i16> %bb to <4 x i32>
491+
%bt1 = zext <4 x i16> %bt to <4 x i32>
492+
%abb = add <4 x i32> %ab1, %bb1
493+
%abt = add <4 x i32> %at1, %bt1
494+
%r = shufflevector <4 x i32> %abb, <4 x i32> %abt, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
495+
store <8 x i32> %r, ptr %p
496+
ret void
497+
}
498+
499+
define void @sext(<8 x i16> %a, <8 x i16> %b, ptr %p) {
500+
; CHECK-LABEL: @sext(
501+
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
502+
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
503+
; CHECK-NEXT: [[BB:%.*]] = shufflevector <8 x i16> [[B:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
504+
; CHECK-NEXT: [[BT:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
505+
; CHECK-NEXT: [[AB1:%.*]] = sext <4 x i16> [[AB]] to <4 x i32>
506+
; CHECK-NEXT: [[AT1:%.*]] = sext <4 x i16> [[AT]] to <4 x i32>
507+
; CHECK-NEXT: [[BB1:%.*]] = sext <4 x i16> [[BB]] to <4 x i32>
508+
; CHECK-NEXT: [[BT1:%.*]] = sext <4 x i16> [[BT]] to <4 x i32>
509+
; CHECK-NEXT: [[ABB:%.*]] = add <4 x i32> [[AB1]], [[BB1]]
510+
; CHECK-NEXT: [[ABT:%.*]] = add <4 x i32> [[AT1]], [[BT1]]
511+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[ABB]], <4 x i32> [[ABT]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
512+
; CHECK-NEXT: store <8 x i32> [[R]], ptr [[P:%.*]], align 32
513+
; CHECK-NEXT: ret void
514+
;
515+
%ab = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
516+
%at = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
517+
%bb = shufflevector <8 x i16> %b, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
518+
%bt = shufflevector <8 x i16> %b, <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
519+
%ab1 = sext <4 x i16> %ab to <4 x i32>
520+
%at1 = sext <4 x i16> %at to <4 x i32>
521+
%bb1 = sext <4 x i16> %bb to <4 x i32>
522+
%bt1 = sext <4 x i16> %bt to <4 x i32>
523+
%abb = add <4 x i32> %ab1, %bb1
524+
%abt = add <4 x i32> %at1, %bt1
525+
%r = shufflevector <4 x i32> %abb, <4 x i32> %abt, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
526+
store <8 x i32> %r, ptr %p
527+
ret void
528+
}
529+
530+
define void @szext(<8 x i32> %a, <8 x i32> %b, ptr %p) {
531+
; CHECK-LABEL: @szext(
532+
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i32> [[A:%.*]], <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
533+
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i32> [[A]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
534+
; CHECK-NEXT: [[AB1:%.*]] = sext <4 x i32> [[AB]] to <4 x i64>
535+
; CHECK-NEXT: [[AT1:%.*]] = zext <4 x i32> [[AT]] to <4 x i64>
536+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i64> [[AB1]], <4 x i64> [[AT1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
537+
; CHECK-NEXT: store <8 x i64> [[R]], ptr [[P:%.*]], align 64
538+
; CHECK-NEXT: ret void
539+
;
540+
%ab = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
541+
%at = shufflevector <8 x i32> %a, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
542+
%ab1 = sext <4 x i32> %ab to <4 x i64>
543+
%at1 = zext <4 x i32> %at to <4 x i64>
544+
%r = shufflevector <4 x i64> %ab1, <4 x i64> %at1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
545+
store <8 x i64> %r, ptr %p
546+
ret void
547+
}
548+
549+
define void @zext_types(<8 x i16> %a, <8 x i32> %b, ptr %p) {
550+
; CHECK-LABEL: @zext_types(
551+
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i16> [[A:%.*]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
552+
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i32> [[B:%.*]], <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
553+
; CHECK-NEXT: [[AB1:%.*]] = zext <4 x i16> [[AB]] to <4 x i64>
554+
; CHECK-NEXT: [[AT1:%.*]] = zext <4 x i32> [[AT]] to <4 x i64>
555+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i64> [[AB1]], <4 x i64> [[AT1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
556+
; CHECK-NEXT: store <8 x i64> [[R]], ptr [[P:%.*]], align 64
557+
; CHECK-NEXT: ret void
558+
;
559+
%ab = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
560+
%at = shufflevector <8 x i32> %b, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
561+
%ab1 = zext <4 x i16> %ab to <4 x i64>
562+
%at1 = zext <4 x i32> %at to <4 x i64>
563+
%r = shufflevector <4 x i64> %ab1, <4 x i64> %at1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
564+
store <8 x i64> %r, ptr %p
565+
ret void
566+
}
567+
568+
define void @trunc(<8 x i64> %a, <8 x i64> %b, ptr %p) {
569+
; CHECK-LABEL: @trunc(
570+
; CHECK-NEXT: [[AB:%.*]] = shufflevector <8 x i64> [[A:%.*]], <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
571+
; CHECK-NEXT: [[AT:%.*]] = shufflevector <8 x i64> [[A]], <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
572+
; CHECK-NEXT: [[ABB1:%.*]] = trunc <4 x i64> [[AB]] to <4 x i32>
573+
; CHECK-NEXT: [[ABT1:%.*]] = trunc <4 x i64> [[AT]] to <4 x i32>
574+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[ABB1]], <4 x i32> [[ABT1]], <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
575+
; CHECK-NEXT: store <8 x i32> [[R]], ptr [[P:%.*]], align 32
576+
; CHECK-NEXT: ret void
577+
;
578+
%ab = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
579+
%at = shufflevector <8 x i64> %a, <8 x i64> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
580+
%abb1 = trunc <4 x i64> %ab to <4 x i32>
581+
%abt1 = trunc <4 x i64> %at to <4 x i32>
582+
%r = shufflevector <4 x i32> %abb1, <4 x i32> %abt1, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7>
583+
store <8 x i32> %r, ptr %p
584+
ret void
585+
}
586+
468587
define <8 x i8> @intrinsics_minmax(<8 x i8> %a, <8 x i8> %b) {
469588
; CHECK-LABEL: @intrinsics_minmax(
470589
; CHECK-NEXT: [[TMP1:%.*]] = call <8 x i8> @llvm.smin.v8i8(<8 x i8> [[A:%.*]], <8 x i8> [[B:%.*]])
@@ -624,4 +743,26 @@ entry:
624743
ret void
625744
}
626745

746+
define <4 x i8> @singleop(<4 x i8> %a, <4 x i8> %b) {
747+
; CHECK-LABEL: @singleop(
748+
; CHECK-NEXT: [[A1:%.*]] = shufflevector <4 x i8> [[A:%.*]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
749+
; CHECK-NEXT: [[B1:%.*]] = shufflevector <4 x i8> [[B:%.*]], <4 x i8> poison, <4 x i32> zeroinitializer
750+
; CHECK-NEXT: [[A2:%.*]] = zext <4 x i8> [[A1]] to <4 x i16>
751+
; CHECK-NEXT: [[B2:%.*]] = zext <4 x i8> [[B1]] to <4 x i16>
752+
; CHECK-NEXT: [[AB:%.*]] = add <4 x i16> [[A2]], [[B2]]
753+
; CHECK-NEXT: [[T:%.*]] = trunc <4 x i16> [[AB]] to <4 x i8>
754+
; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x i8> [[T]], <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
755+
; CHECK-NEXT: ret <4 x i8> [[R]]
756+
;
757+
%a1 = shufflevector <4 x i8> %a, <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
758+
%b1 = shufflevector <4 x i8> %b, <4 x i8> poison, <4 x i32> <i32 0, i32 0, i32 0, i32 0>
759+
%a2 = zext <4 x i8> %a1 to <4 x i16>
760+
%b2 = zext <4 x i8> %b1 to <4 x i16>
761+
%ab = add <4 x i16> %a2, %b2
762+
%t = trunc <4 x i16> %ab to <4 x i8>
763+
%r = shufflevector <4 x i8> %t, <4 x i8> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
764+
ret <4 x i8> %r
765+
}
766+
767+
627768
declare void @use(<4 x i8>)

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