Skip to content

Commit 3e60693

Browse files
committed
[RISCV][GISel] Rename PartialMappingIdx and ValueMappingsIdx to use register bank name with B suffix. NFC
PartialMappingIdx refers to an entry in the PartMappings table that includes a RegBank and a size. So I think the PartialMappingIdx should be named using the name of the register bank concatenated with the size. So the indices are now PMI_GPRB32, PMI_GPRB64, PMI_FPRB32, PMI_FPRB64.
1 parent 8c53cfd commit 3e60693

File tree

1 file changed

+23
-22
lines changed

1 file changed

+23
-22
lines changed

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 23 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -32,39 +32,39 @@ const RegisterBankInfo::PartialMapping PartMappings[] = {
3232
};
3333

3434
enum PartialMappingIdx {
35-
PMI_GPR32 = 0,
36-
PMI_GPR64 = 1,
37-
PMI_FPR32 = 2,
38-
PMI_FPR64 = 3,
35+
PMI_GPRB32 = 0,
36+
PMI_GPRB64 = 1,
37+
PMI_FPRB32 = 2,
38+
PMI_FPRB64 = 3,
3939
};
4040

4141
const RegisterBankInfo::ValueMapping ValueMappings[] = {
4242
// Invalid value mapping.
4343
{nullptr, 0},
4444
// Maximum 3 GPR operands; 32 bit.
45-
{&PartMappings[PMI_GPR32], 1},
46-
{&PartMappings[PMI_GPR32], 1},
47-
{&PartMappings[PMI_GPR32], 1},
45+
{&PartMappings[PMI_GPRB32], 1},
46+
{&PartMappings[PMI_GPRB32], 1},
47+
{&PartMappings[PMI_GPRB32], 1},
4848
// Maximum 3 GPR operands; 64 bit.
49-
{&PartMappings[PMI_GPR64], 1},
50-
{&PartMappings[PMI_GPR64], 1},
51-
{&PartMappings[PMI_GPR64], 1},
49+
{&PartMappings[PMI_GPRB64], 1},
50+
{&PartMappings[PMI_GPRB64], 1},
51+
{&PartMappings[PMI_GPRB64], 1},
5252
// Maximum 3 FPR operands; 32 bit.
53-
{&PartMappings[PMI_FPR32], 1},
54-
{&PartMappings[PMI_FPR32], 1},
55-
{&PartMappings[PMI_FPR32], 1},
53+
{&PartMappings[PMI_FPRB32], 1},
54+
{&PartMappings[PMI_FPRB32], 1},
55+
{&PartMappings[PMI_FPRB32], 1},
5656
// Maximum 3 FPR operands; 64 bit.
57-
{&PartMappings[PMI_FPR64], 1},
58-
{&PartMappings[PMI_FPR64], 1},
59-
{&PartMappings[PMI_FPR64], 1},
57+
{&PartMappings[PMI_FPRB64], 1},
58+
{&PartMappings[PMI_FPRB64], 1},
59+
{&PartMappings[PMI_FPRB64], 1},
6060
};
6161

6262
enum ValueMappingsIdx {
6363
InvalidIdx = 0,
64-
GPR32Idx = 1,
65-
GPR64Idx = 4,
66-
FPR32Idx = 7,
67-
FPR64Idx = 10,
64+
GPRB32Idx = 1,
65+
GPRB64Idx = 4,
66+
FPRB32Idx = 7,
67+
FPRB64Idx = 10,
6868
};
6969
} // namespace RISCV
7070
} // namespace llvm
@@ -105,7 +105,7 @@ RISCVRegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
105105

106106
static const RegisterBankInfo::ValueMapping *getFPValueMapping(unsigned Size) {
107107
assert(Size == 32 || Size == 64);
108-
unsigned Idx = Size == 64 ? RISCV::FPR64Idx : RISCV::FPR32Idx;
108+
unsigned Idx = Size == 64 ? RISCV::FPRB64Idx : RISCV::FPRB32Idx;
109109
return &RISCV::ValueMappings[Idx];
110110
}
111111

@@ -129,7 +129,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
129129

130130
unsigned NumOperands = MI.getNumOperands();
131131
const ValueMapping *GPRValueMapping =
132-
&RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPR64Idx : RISCV::GPR32Idx];
132+
&RISCV::ValueMappings[GPRSize == 64 ? RISCV::GPRB64Idx
133+
: RISCV::GPRB32Idx];
133134
const ValueMapping *OperandsMapping = GPRValueMapping;
134135

135136
switch (Opc) {

0 commit comments

Comments
 (0)