Merged main:241c290ad73f into amd-gfx:77eb6cdceaa5

Local branch amd-gfx 77eb6cd Merged main:f9906508bc4f into amd-gfx:aab4d6b3f6fc
Remote branch main 241c290 Reland [LLD] [COFF] Dont try to detect MSVC installations in mingw mode

Author: SC llvm team

lld/COFF/Driver.cpp

@@ -1588,13 +1588,25 @@ void LinkerDriver::linkerMain(ArrayRef<const char *> argsArr) {
   {
     llvm::TimeTraceScope timeScope2("Search paths");
     searchPaths.emplace_back("");
-    // Prefer the Clang provided builtins over the ones bundled with MSVC.
-    addClangLibSearchPaths(argsArr[0]);
+    if (!config->mingw) {
+      // Prefer the Clang provided builtins over the ones bundled with MSVC.
+      // In MinGW mode, the compiler driver passes the necessary libpath
+      // options explicitly.
+      addClangLibSearchPaths(argsArr[0]);
+    }
     for (auto *arg : args.filtered(OPT_libpath))
       searchPaths.push_back(arg->getValue());
-    detectWinSysRoot(args);
-    if (!args.hasArg(OPT_lldignoreenv) && !args.hasArg(OPT_winsysroot))
-      addLibSearchPaths();
+    if (!config->mingw) {
+      // Don't automatically deduce the lib path from the environment or MSVC
+      // installations when operating in mingw mode. (This also makes LLD ignore
+      // winsysroot and vctoolsdir arguments.)
+      detectWinSysRoot(args);
+      if (!args.hasArg(OPT_lldignoreenv) && !args.hasArg(OPT_winsysroot))
+        addLibSearchPaths();
+    } else {
+      if (args.hasArg(OPT_vctoolsdir, OPT_winsysroot))
+        warn("ignoring /vctoolsdir or /winsysroot flags in MinGW mode");
+    }
   }
 
   // Handle /ignore

lld/test/COFF/winsysroot.test

@@ -49,5 +49,12 @@ NO64: could not open 'std64.lib'
 NO32: could not open 'std32.lib'
 
 Check that when /winsysroot is specified, %LIB% is ignored.
-# RUN: env LIB=foo.dir/sysroot/VC/Tools/MSVC/1.1.1.1/lib/x86 not lld-link %t.obj /winsysroot:%t.dir/doesnotexist /defaultlib:std32 2>&1 | FileCheck -check-prefix=LIBIGNORED %s
+# RUN: env LIB=%t.dir/sysroot/VC/Tools/MSVC/1.1.1.1/lib/x86 not lld-link %t.obj /winsysroot:%t.dir/doesnotexist /defaultlib:std32 2>&1 | FileCheck -check-prefix=LIBIGNORED %s
 LIBIGNORED: could not open 'std32.lib'
+
+Check that when -lldmingw is specified, %LIB% is ignored.
+# RUN: env LIB=%t.dir/sysroot/VC/Tools/MSVC/1.1.1.1/lib/x86 not lld-link -lldmingw %t.obj /defaultlib:std32 2>&1 | FileCheck -check-prefix=LIBIGNORED_MINGW %s
+LIBIGNORED_MINGW: could not open 'libstd32.a'
+
+# RUN: not lld-link -lldmingw %t.obj /defaultlib:std32 /winsysroot:%t.dir/sysroot 2>&1 | FileCheck -check-prefix=IGNORED_ARG %s
+IGNORED_ARG: warning: ignoring /vctoolsdir or /winsysroot flags in MinGW mode

lldb/docs/lldb-gdb-remote.txt

@@ -581,11 +581,15 @@ read packet: <binary data>/E<error code>;AAAAAAAAA
 //  will get picked up automatically, and allows registers to change
 //  depending on the actual CPU type that is used.
 //
-//  NB: As of summer 2015, lldb can get register information from the
-//  "qXfer:features:read:target.xml" FSF gdb standard register packet
-//  where the stub provides register definitions in an XML file.
+//  NB: qRegisterInfo is deprecated in favor of the standard gdb remote
+//  serial protocol register description method, 
+//  "qXfer:features:read:target.xml".
 //  If qXfer:features:read:target.xml is supported, qRegisterInfo does
-//  not need to be implemented.
+//  not need to be implemented.  The target.xml format is used by most
+//  gdb RSP stubs whereas qRegisterInfo was an lldb-only design.
+//  qRegisterInfo requires one packet per register and can have undesirable
+//  performance costs at the start of a debug session, whereas target.xml
+//  may be able to describe all registers in a single packet.
 //----------------------------------------------------------------------
 
 With LLDB, for register information, remote GDB servers can add

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 478254
+#define LLVM_MAIN_REVISION 478259
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

@@ -223,7 +223,7 @@ unsigned RISCVInstrumentManager::getSchedClassID(
   unsigned short Opcode = MCI.getOpcode();
   unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
 
-  // Unpack all possible RISCV instruments from IVec.
+  // Unpack all possible RISC-V instruments from IVec.
   RISCVLMULInstrument *LI = nullptr;
   RISCVSEWInstrument *SI = nullptr;
   for (auto &I : IVec) {

llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

@@ -1,4 +1,4 @@
-//===-- RISCVAsmBackend.cpp - RISCV Assembler Backend ---------------------===//
+//===-- RISCVAsmBackend.cpp - RISC-V Assembler Backend --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

@@ -1,4 +1,4 @@
-//===-- RISCVFixupKinds.h - RISCV Specific Fixup Entries --------*- C++ -*-===//
+//===-- RISCVFixupKinds.h - RISC-V Specific Fixup Entries -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.

llvm/lib/Target/RISCV/RISCVGISel.td

@@ -1,4 +1,4 @@
-//===-- RISCVGIsel.td - RISCV GlobalISel Patterns ----------*- tablegen -*-===//
+//===-- RISCVGIsel.td - RISC-V GlobalISel Patterns ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -5232,7 +5232,7 @@ static SDValue lowerFMAXIMUM_FMINIMUM(SDValue Op, SelectionDAG &DAG,
   return Res;
 }
 
-/// Get a RISCV target specified VL op for a given SDNode.
+/// Get a RISC-V target specified VL op for a given SDNode.
 static unsigned getRISCVVLOp(SDValue Op) {
 #define OP_CASE(NODE)                                                          \
   case ISD::NODE:                                                              \

llvm/lib/Target/RISCV/RISCVMoveMerger.cpp

@@ -1,4 +1,4 @@
-//===-- RISCVMoveMerger.cpp - RISCV move merge pass -----------------------===//
+//===-- RISCVMoveMerger.cpp - RISC-V move merge pass ----------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.

llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp

@@ -1,4 +1,4 @@
-//===------- RISCVPushPopOptimizer.cpp - RISCV Push/Pop opt. pass ---------===//
+//===------- RISCVPushPopOptimizer.cpp - RISC-V Push/Pop opt. pass --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.

llvm/lib/Transforms/IPO/AttributorAttributes.cpp

@@ -1200,6 +1200,11 @@ struct AAPointerInfoImpl
         A, this, IRPosition::function(Scope), DepClassTy::OPTIONAL,
         IsKnownNoRecurse);
 
+    // TODO: Use reaching kernels from AAKernelInfo (or move it to
+    // AAExecutionDomain) such that we allow scopes other than kernels as long
+    // as the reaching kernels are disjoint.
+    bool InstInKernel = Scope.hasFnAttribute("kernel");
+    bool ObjHasKernelLifetime = false;
     const bool UseDominanceReasoning =
         FindInterferingWrites && IsKnownNoRecurse;
     const DominatorTree *DT =
@@ -1232,6 +1237,7 @@ struct AAPointerInfoImpl
       // If the alloca containing function is not recursive the alloca
       // must be dead in the callee.
       const Function *AIFn = AI->getFunction();
+      ObjHasKernelLifetime = AIFn->hasFnAttribute("kernel");
       bool IsKnownNoRecurse;
       if (AA::hasAssumedIRAttr<Attribute::NoRecurse>(
               A, this, IRPosition::function(*AIFn), DepClassTy::OPTIONAL,
@@ -1241,7 +1247,8 @@ struct AAPointerInfoImpl
     } else if (auto *GV = dyn_cast<GlobalValue>(&getAssociatedValue())) {
       // If the global has kernel lifetime we can stop if we reach a kernel
       // as it is "dead" in the (unknown) callees.
-      if (HasKernelLifetime(GV, *GV->getParent()))
+      ObjHasKernelLifetime = HasKernelLifetime(GV, *GV->getParent());
+      if (ObjHasKernelLifetime)
         IsLiveInCalleeCB = [](const Function &Fn) {
           return !Fn.hasFnAttribute("kernel");
         };
@@ -1252,6 +1259,15 @@ struct AAPointerInfoImpl
     AA::InstExclusionSetTy ExclusionSet;
 
     auto AccessCB = [&](const Access &Acc, bool Exact) {
+      Function *AccScope = Acc.getRemoteInst()->getFunction();
+      bool AccInSameScope = AccScope == &Scope;
+
+      // If the object has kernel lifetime we can ignore accesses only reachable
+      // by other kernels. For now we only skip accesses *in* other kernels.
+      if (InstInKernel && ObjHasKernelLifetime && !AccInSameScope &&
+          AccScope->hasFnAttribute("kernel"))
+        return true;
+
       if (Exact && Acc.isMustAccess() && Acc.getRemoteInst() != &I) {
         if (Acc.isWrite() || (isa<LoadInst>(I) && Acc.isWriteOrAssumption()))
           ExclusionSet.insert(Acc.getRemoteInst());
@@ -1262,8 +1278,7 @@ struct AAPointerInfoImpl
         return true;
 
       bool Dominates = FindInterferingWrites && DT && Exact &&
-                       Acc.isMustAccess() &&
-                       (Acc.getRemoteInst()->getFunction() == &Scope) &&
+                       Acc.isMustAccess() && AccInSameScope &&
                        DT->dominates(Acc.getRemoteInst(), &I);
       if (Dominates)
         DominatingWrites.insert(&Acc);

llvm/test/Transforms/Attributor/value-simplify-gpu.ll

@@ -8,11 +8,13 @@ target triple = "amdgcn-amd-amdhsa"
 @ReachableKernel = internal addrspace(3) global i32 3, align 4
 @UnreachableKernel = internal addrspace(3) global i32 42, align 4
 @ReachableKernelAS0 = internal global i32 7, align 4
+@AS3OneKernelAtATime = internal addrspace(3) global i32 42, align 4
 
 ;.
 ; CHECK: @[[REACHABLEKERNEL:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global i32 3, align 4
 ; CHECK: @[[UNREACHABLEKERNEL:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global i32 42, align 4
 ; CHECK: @[[REACHABLEKERNELAS0:[a-zA-Z0-9_$"\\.-]+]] = internal global i32 7, align 4
+; CHECK: @[[AS3ONEKERNELATATIME:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global i32 42, align 4
 ; CHECK: @[[REACHABLENONKERNEL:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global i32 0, align 4
 ; CHECK: @[[UNREACHABLENONKERNEL:[a-zA-Z0-9_$"\\.-]+]] = internal addrspace(3) global i32 0, align 4
 ;.
@@ -354,6 +356,77 @@ entry:
   ret void
 }
 
+define dso_local void @kernel2(i32 %C) norecurse "kernel" {
+; TUNIT: Function Attrs: norecurse nosync nounwind
+; TUNIT-LABEL: define {{[^@]+}}@kernel2
+; TUNIT-SAME: (i32 [[C:%.*]]) #[[ATTR0]] {
+; TUNIT-NEXT:    [[I:%.*]] = icmp eq i32 [[C]], 42
+; TUNIT-NEXT:    br i1 [[I]], label [[T:%.*]], label [[F:%.*]]
+; TUNIT:       t:
+; TUNIT-NEXT:    store i32 333, ptr addrspace(3) @AS3OneKernelAtATime, align 4
+; TUNIT-NEXT:    br label [[F]]
+; TUNIT:       f:
+; TUNIT-NEXT:    [[L:%.*]] = load i32, ptr addrspace(3) @AS3OneKernelAtATime, align 4
+; TUNIT-NEXT:    call void @use(i32 noundef [[L]], i32 noundef [[L]], i32 noundef [[L]]) #[[ATTR7]]
+; TUNIT-NEXT:    ret void
+;
+; CGSCC: Function Attrs: norecurse nosync nounwind
+; CGSCC-LABEL: define {{[^@]+}}@kernel2
+; CGSCC-SAME: (i32 [[C:%.*]]) #[[ATTR0]] {
+; CGSCC-NEXT:    [[I:%.*]] = icmp eq i32 [[C]], 42
+; CGSCC-NEXT:    br i1 [[I]], label [[T:%.*]], label [[F:%.*]]
+; CGSCC:       t:
+; CGSCC-NEXT:    store i32 333, ptr addrspace(3) @AS3OneKernelAtATime, align 4
+; CGSCC-NEXT:    br label [[F]]
+; CGSCC:       f:
+; CGSCC-NEXT:    [[L:%.*]] = load i32, ptr addrspace(3) @AS3OneKernelAtATime, align 4
+; CGSCC-NEXT:    call void @use(i32 noundef [[L]], i32 noundef [[L]], i32 noundef [[L]]) #[[ATTR4]]
+; CGSCC-NEXT:    ret void
+;
+  %i = icmp eq i32 %C, 42
+  br i1 %i, label %t, label %f
+t:
+  store i32 333, ptr addrspace(3) @AS3OneKernelAtATime
+  br label %f
+f:
+  %l = load i32, ptr addrspace(3) @AS3OneKernelAtATime
+  call void @use(i32 %l,i32 %l, i32 %l)
+  ret void
+}
+
+define dso_local void @kernel3(i32 %C) norecurse "kernel" {
+; TUNIT: Function Attrs: norecurse nosync nounwind
+; TUNIT-LABEL: define {{[^@]+}}@kernel3
+; TUNIT-SAME: (i32 [[C:%.*]]) #[[ATTR0]] {
+; TUNIT-NEXT:    [[I:%.*]] = icmp eq i32 [[C]], 42
+; TUNIT-NEXT:    br i1 [[I]], label [[T:%.*]], label [[F:%.*]]
+; TUNIT:       t:
+; TUNIT-NEXT:    call void @use(i32 noundef 42, i32 noundef 42, i32 noundef 42) #[[ATTR7]]
+; TUNIT-NEXT:    ret void
+; TUNIT:       f:
+; TUNIT-NEXT:    ret void
+;
+; CGSCC: Function Attrs: norecurse nosync nounwind
+; CGSCC-LABEL: define {{[^@]+}}@kernel3
+; CGSCC-SAME: (i32 [[C:%.*]]) #[[ATTR0]] {
+; CGSCC-NEXT:    [[I:%.*]] = icmp eq i32 [[C]], 42
+; CGSCC-NEXT:    br i1 [[I]], label [[T:%.*]], label [[F:%.*]]
+; CGSCC:       t:
+; CGSCC-NEXT:    call void @use(i32 noundef 42, i32 noundef 42, i32 noundef 42) #[[ATTR4]]
+; CGSCC-NEXT:    ret void
+; CGSCC:       f:
+; CGSCC-NEXT:    ret void
+;
+  %i = icmp eq i32 %C, 42
+  br i1 %i, label %t, label %f
+t:
+  %l = load i32, ptr addrspace(3) @AS3OneKernelAtATime
+  call void @use(i32 %l,i32 %l, i32 %l)
+  ret void
+f:
+  ret void
+}
+
 declare dso_local void @use(i32, i32, i32) nosync norecurse nounwind
 
 ;.