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[RISCV] Don't promote i32 and/or/xor with -riscv-experimental-rv64-legal-i32.
Some test improvements, but also some regressions that need to be fixed.
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11 files changed

+123
-151
lines changed

11 files changed

+123
-151
lines changed

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -81,20 +81,9 @@ def : Pat<(XLenVT (sub GPR:$rs1, simm12Plus1:$imm)),
8181
(ADDI GPR:$rs1, (NegImm simm12Plus1:$imm))>;
8282

8383
let Predicates = [IsRV64] in {
84-
def : Pat<(i32 (and GPR:$rs1, GPR:$rs2)), (AND GPR:$rs1, GPR:$rs2)>;
85-
def : Pat<(i32 (or GPR:$rs1, GPR:$rs2)), (OR GPR:$rs1, GPR:$rs2)>;
86-
def : Pat<(i32 (xor GPR:$rs1, GPR:$rs2)), (XOR GPR:$rs1, GPR:$rs2)>;
87-
8884
def : Pat<(i32 (sub GPR:$rs1, simm12Plus1i32:$imm)),
8985
(ADDIW GPR:$rs1, (i64 (NegImm $imm)))>;
9086

91-
def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
92-
(ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
93-
def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
94-
(ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
95-
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
96-
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
97-
9887
def : Pat<(i32 (shl GPR:$rs1, (i32 GPR:$rs2))), (SLLW GPR:$rs1, GPR:$rs2)>;
9988
def : Pat<(i32 (sra GPR:$rs1, (i32 GPR:$rs2))), (SRAW GPR:$rs1, GPR:$rs2)>;
10089
def : Pat<(i32 (srl GPR:$rs1, (i32 GPR:$rs2))), (SRLW GPR:$rs1, GPR:$rs2)>;

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -275,16 +275,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
275275
if (Subtarget.is64Bit()) {
276276
setOperationAction(ISD::EH_DWARF_CFA, MVT::i64, Custom);
277277

278-
if (!RV64LegalI32)
278+
if (!RV64LegalI32) {
279279
setOperationAction(ISD::LOAD, MVT::i32, Custom);
280-
281-
if (RV64LegalI32)
282-
setOperationAction({ISD::AND, ISD::OR, ISD::XOR}, MVT::i32, Promote);
283-
else
284280
setOperationAction({ISD::ADD, ISD::SUB, ISD::SHL, ISD::SRA, ISD::SRL},
285281
MVT::i32, Custom);
286-
287-
if (!RV64LegalI32) {
288282
setOperationAction(ISD::SADDO, MVT::i32, Custom);
289283
setOperationAction({ISD::UADDO, ISD::USUBO, ISD::UADDSAT, ISD::USUBSAT},
290284
MVT::i32, Custom);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2023,12 +2023,21 @@ def : Pat<(trunc GPR:$src), (COPY GPR:$src)>;
20232023

20242024
def : PatGprGpr<add, ADDW, i32, i32>;
20252025
def : PatGprGpr<sub, SUBW, i32, i32>;
2026+
def : PatGprGpr<and, AND, i32, i32>;
2027+
def : PatGprGpr<or, OR, i32, i32>;
2028+
def : PatGprGpr<xor, XOR, i32, i32>;
20262029
def : PatGprGpr<shiftopw<shl>, SLLW, i32, i64>;
20272030
def : PatGprGpr<shiftopw<srl>, SRLW, i32, i64>;
20282031
def : PatGprGpr<shiftopw<sra>, SRAW, i32, i64>;
20292032

20302033
def : Pat<(i32 (add GPR:$rs1, simm12i32:$imm)),
20312034
(ADDIW GPR:$rs1, (i64 (as_i64imm $imm)))>;
2035+
def : Pat<(i32 (and GPR:$rs1, simm12i32:$imm)),
2036+
(ANDI GPR:$rs1, (i64 (as_i64imm $imm)))>;
2037+
def : Pat<(i32 (or GPR:$rs1, simm12i32:$imm)),
2038+
(ORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
2039+
def : Pat<(i32 (xor GPR:$rs1, simm12i32:$imm)),
2040+
(XORI GPR:$rs1, (i64 (as_i64imm $imm)))>;
20322041

20332042
def : PatGprImm<shl, SLLIW, uimm5, i32>;
20342043
def : PatGprImm<srl, SRLIW, uimm5, i32>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -827,6 +827,10 @@ def : Pat<(i32 (sext_inreg GPR:$rs1, i16)), (SEXT_H GPR:$rs1)>;
827827
} // Predicates = [HasStdExtZbb, IsRV64]
828828

829829
let Predicates = [HasStdExtZbbOrZbkb, IsRV64] in {
830+
def : Pat<(i32 (and GPR:$rs1, (not GPR:$rs2))), (ANDN GPR:$rs1, GPR:$rs2)>;
831+
def : Pat<(i32 (or GPR:$rs1, (not GPR:$rs2))), (ORN GPR:$rs1, GPR:$rs2)>;
832+
def : Pat<(i32 (xor GPR:$rs1, (not GPR:$rs2))), (XNOR GPR:$rs1, GPR:$rs2)>;
833+
830834
def : PatGprGpr<shiftopw<rotl>, ROLW, i32, i64>;
831835
def : PatGprGpr<shiftopw<rotr>, RORW, i32, i64>;
832836
def : PatGprImm<rotr, RORIW, uimm5, i32>;

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/div.ll

Lines changed: 22 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -184,14 +184,14 @@ define i8 @udiv8_constant(i8 %a) nounwind {
184184
define i8 @udiv8_pow2(i8 %a) nounwind {
185185
; RV64I-LABEL: udiv8_pow2:
186186
; RV64I: # %bb.0:
187-
; RV64I-NEXT: andi a0, a0, 248
188-
; RV64I-NEXT: srliw a0, a0, 3
187+
; RV64I-NEXT: slli a0, a0, 56
188+
; RV64I-NEXT: srli a0, a0, 59
189189
; RV64I-NEXT: ret
190190
;
191191
; RV64IM-LABEL: udiv8_pow2:
192192
; RV64IM: # %bb.0:
193-
; RV64IM-NEXT: andi a0, a0, 248
194-
; RV64IM-NEXT: srliw a0, a0, 3
193+
; RV64IM-NEXT: slli a0, a0, 56
194+
; RV64IM-NEXT: srli a0, a0, 59
195195
; RV64IM-NEXT: ret
196196
%1 = udiv i8 %a, 8
197197
ret i8 %1
@@ -260,11 +260,10 @@ define i16 @udiv16_constant(i16 %a) nounwind {
260260
;
261261
; RV64IM-LABEL: udiv16_constant:
262262
; RV64IM: # %bb.0:
263+
; RV64IM-NEXT: lui a1, 52429
264+
; RV64IM-NEXT: slli a1, a1, 4
263265
; RV64IM-NEXT: slli a0, a0, 48
264-
; RV64IM-NEXT: srli a0, a0, 48
265-
; RV64IM-NEXT: lui a1, 13
266-
; RV64IM-NEXT: addi a1, a1, -819
267-
; RV64IM-NEXT: mul a0, a0, a1
266+
; RV64IM-NEXT: mulhu a0, a0, a1
268267
; RV64IM-NEXT: srliw a0, a0, 18
269268
; RV64IM-NEXT: ret
270269
%1 = udiv i16 %a, 5
@@ -275,15 +274,13 @@ define i16 @udiv16_pow2(i16 %a) nounwind {
275274
; RV64I-LABEL: udiv16_pow2:
276275
; RV64I: # %bb.0:
277276
; RV64I-NEXT: slli a0, a0, 48
278-
; RV64I-NEXT: srli a0, a0, 48
279-
; RV64I-NEXT: srliw a0, a0, 3
277+
; RV64I-NEXT: srli a0, a0, 51
280278
; RV64I-NEXT: ret
281279
;
282280
; RV64IM-LABEL: udiv16_pow2:
283281
; RV64IM: # %bb.0:
284282
; RV64IM-NEXT: slli a0, a0, 48
285-
; RV64IM-NEXT: srli a0, a0, 48
286-
; RV64IM-NEXT: srliw a0, a0, 3
283+
; RV64IM-NEXT: srli a0, a0, 51
287284
; RV64IM-NEXT: ret
288285
%1 = udiv i16 %a, 8
289286
ret i16 %1
@@ -304,8 +301,9 @@ define i16 @udiv16_constant_lhs(i16 %a) nounwind {
304301
;
305302
; RV64IM-LABEL: udiv16_constant_lhs:
306303
; RV64IM: # %bb.0:
307-
; RV64IM-NEXT: slli a0, a0, 48
308-
; RV64IM-NEXT: srli a0, a0, 48
304+
; RV64IM-NEXT: lui a1, 16
305+
; RV64IM-NEXT: addi a1, a1, -1
306+
; RV64IM-NEXT: and a0, a0, a1
309307
; RV64IM-NEXT: li a1, 10
310308
; RV64IM-NEXT: divuw a0, a1, a0
311309
; RV64IM-NEXT: ret
@@ -536,8 +534,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
536534
; RV64IM-NEXT: li a1, 103
537535
; RV64IM-NEXT: mul a0, a0, a1
538536
; RV64IM-NEXT: sraiw a1, a0, 9
539-
; RV64IM-NEXT: srliw a0, a0, 15
540-
; RV64IM-NEXT: andi a0, a0, 1
537+
; RV64IM-NEXT: slli a0, a0, 48
538+
; RV64IM-NEXT: srli a0, a0, 63
541539
; RV64IM-NEXT: addw a0, a1, a0
542540
; RV64IM-NEXT: ret
543541
%1 = sdiv i8 %a, 5
@@ -549,8 +547,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
549547
; RV64I: # %bb.0:
550548
; RV64I-NEXT: slli a1, a0, 24
551549
; RV64I-NEXT: sraiw a1, a1, 24
552-
; RV64I-NEXT: srliw a1, a1, 12
553-
; RV64I-NEXT: andi a1, a1, 7
550+
; RV64I-NEXT: slli a1, a1, 49
551+
; RV64I-NEXT: srli a1, a1, 61
554552
; RV64I-NEXT: add a0, a0, a1
555553
; RV64I-NEXT: slli a0, a0, 24
556554
; RV64I-NEXT: sraiw a0, a0, 27
@@ -560,8 +558,8 @@ define i8 @sdiv8_pow2(i8 %a) nounwind {
560558
; RV64IM: # %bb.0:
561559
; RV64IM-NEXT: slli a1, a0, 24
562560
; RV64IM-NEXT: sraiw a1, a1, 24
563-
; RV64IM-NEXT: srliw a1, a1, 12
564-
; RV64IM-NEXT: andi a1, a1, 7
561+
; RV64IM-NEXT: slli a1, a1, 49
562+
; RV64IM-NEXT: srli a1, a1, 61
565563
; RV64IM-NEXT: add a0, a0, a1
566564
; RV64IM-NEXT: slli a0, a0, 24
567565
; RV64IM-NEXT: sraiw a0, a0, 27
@@ -653,8 +651,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
653651
; RV64I: # %bb.0:
654652
; RV64I-NEXT: slli a1, a0, 16
655653
; RV64I-NEXT: sraiw a1, a1, 16
656-
; RV64I-NEXT: srliw a1, a1, 28
657-
; RV64I-NEXT: andi a1, a1, 7
654+
; RV64I-NEXT: slli a1, a1, 33
655+
; RV64I-NEXT: srli a1, a1, 61
658656
; RV64I-NEXT: add a0, a0, a1
659657
; RV64I-NEXT: slli a0, a0, 16
660658
; RV64I-NEXT: sraiw a0, a0, 19
@@ -664,8 +662,8 @@ define i16 @sdiv16_pow2(i16 %a) nounwind {
664662
; RV64IM: # %bb.0:
665663
; RV64IM-NEXT: slli a1, a0, 16
666664
; RV64IM-NEXT: sraiw a1, a1, 16
667-
; RV64IM-NEXT: srliw a1, a1, 28
668-
; RV64IM-NEXT: andi a1, a1, 7
665+
; RV64IM-NEXT: slli a1, a1, 33
666+
; RV64IM-NEXT: srli a1, a1, 61
669667
; RV64IM-NEXT: add a0, a0, a1
670668
; RV64IM-NEXT: slli a0, a0, 16
671669
; RV64IM-NEXT: sraiw a0, a0, 19

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rem.ll

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -330,8 +330,9 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
330330
;
331331
; RV64IM-LABEL: urem16_constant_lhs:
332332
; RV64IM: # %bb.0:
333-
; RV64IM-NEXT: slli a0, a0, 48
334-
; RV64IM-NEXT: srli a0, a0, 48
333+
; RV64IM-NEXT: lui a1, 16
334+
; RV64IM-NEXT: addi a1, a1, -1
335+
; RV64IM-NEXT: and a0, a0, a1
335336
; RV64IM-NEXT: li a1, 10
336337
; RV64IM-NEXT: remuw a0, a1, a0
337338
; RV64IM-NEXT: ret

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -238,10 +238,10 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
238238
; RV64XTHEADBB: # %bb.0:
239239
; RV64XTHEADBB-NEXT: th.extu a1, a0, 31, 0
240240
; RV64XTHEADBB-NEXT: th.ff1 a1, a1
241-
; RV64XTHEADBB-NEXT: addi a1, a1, -32
241+
; RV64XTHEADBB-NEXT: addiw a1, a1, -32
242242
; RV64XTHEADBB-NEXT: xori a1, a1, 31
243243
; RV64XTHEADBB-NEXT: snez a0, a0
244-
; RV64XTHEADBB-NEXT: addi a0, a0, -1
244+
; RV64XTHEADBB-NEXT: addiw a0, a0, -1
245245
; RV64XTHEADBB-NEXT: or a0, a0, a1
246246
; RV64XTHEADBB-NEXT: ret
247247
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true)
@@ -749,8 +749,9 @@ define i64 @no_sexth_i64(i64 %a) nounwind {
749749
define i32 @zexth_i32(i32 %a) nounwind {
750750
; RV64I-LABEL: zexth_i32:
751751
; RV64I: # %bb.0:
752-
; RV64I-NEXT: slli a0, a0, 48
753-
; RV64I-NEXT: srli a0, a0, 48
752+
; RV64I-NEXT: lui a1, 16
753+
; RV64I-NEXT: addiw a1, a1, -1
754+
; RV64I-NEXT: and a0, a0, a1
754755
; RV64I-NEXT: ret
755756
;
756757
; RV64XTHEADBB-LABEL: zexth_i32:

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb-zbkb.ll

Lines changed: 12 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -71,16 +71,11 @@ define i64 @orn_i64(i64 %a, i64 %b) nounwind {
7171
}
7272

7373
define signext i32 @xnor_i32(i32 signext %a, i32 signext %b) nounwind {
74-
; RV64I-LABEL: xnor_i32:
75-
; RV64I: # %bb.0:
76-
; RV64I-NEXT: xor a0, a0, a1
77-
; RV64I-NEXT: not a0, a0
78-
; RV64I-NEXT: ret
79-
;
80-
; RV64ZBB-ZBKB-LABEL: xnor_i32:
81-
; RV64ZBB-ZBKB: # %bb.0:
82-
; RV64ZBB-ZBKB-NEXT: xnor a0, a0, a1
83-
; RV64ZBB-ZBKB-NEXT: ret
74+
; CHECK-LABEL: xnor_i32:
75+
; CHECK: # %bb.0:
76+
; CHECK-NEXT: xor a0, a0, a1
77+
; CHECK-NEXT: not a0, a0
78+
; CHECK-NEXT: ret
8479
%neg = xor i32 %a, -1
8580
%xor = xor i32 %neg, %b
8681
ret i32 %xor
@@ -446,8 +441,8 @@ define i64 @not_shl_one_i64(i64 %x) {
446441
define i8 @srli_i8(i8 %a) nounwind {
447442
; CHECK-LABEL: srli_i8:
448443
; CHECK: # %bb.0:
449-
; CHECK-NEXT: andi a0, a0, 192
450-
; CHECK-NEXT: srliw a0, a0, 6
444+
; CHECK-NEXT: slli a0, a0, 56
445+
; CHECK-NEXT: srli a0, a0, 62
451446
; CHECK-NEXT: ret
452447
%1 = lshr i8 %a, 6
453448
ret i8 %1
@@ -480,25 +475,11 @@ define i8 @srai_i8(i8 %a) nounwind {
480475
; We could use zext.h+srli, but slli+srli offers more opportunities for
481476
; comppressed instructions.
482477
define i16 @srli_i16(i16 %a) nounwind {
483-
; RV64I-LABEL: srli_i16:
484-
; RV64I: # %bb.0:
485-
; RV64I-NEXT: slli a0, a0, 48
486-
; RV64I-NEXT: srli a0, a0, 48
487-
; RV64I-NEXT: srliw a0, a0, 6
488-
; RV64I-NEXT: ret
489-
;
490-
; RV64ZBB-LABEL: srli_i16:
491-
; RV64ZBB: # %bb.0:
492-
; RV64ZBB-NEXT: zext.h a0, a0
493-
; RV64ZBB-NEXT: srliw a0, a0, 6
494-
; RV64ZBB-NEXT: ret
495-
;
496-
; RV64ZBKB-LABEL: srli_i16:
497-
; RV64ZBKB: # %bb.0:
498-
; RV64ZBKB-NEXT: slli a0, a0, 48
499-
; RV64ZBKB-NEXT: srli a0, a0, 48
500-
; RV64ZBKB-NEXT: srliw a0, a0, 6
501-
; RV64ZBKB-NEXT: ret
478+
; CHECK-LABEL: srli_i16:
479+
; CHECK: # %bb.0:
480+
; CHECK-NEXT: slli a0, a0, 48
481+
; CHECK-NEXT: srli a0, a0, 54
482+
; CHECK-NEXT: ret
502483
%1 = lshr i16 %a, 6
503484
ret i16 %1
504485
}

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -944,13 +944,16 @@ define i64 @abs_i64(i64 %x) {
944944
define i32 @zexth_i32(i32 %a) nounwind {
945945
; RV64I-LABEL: zexth_i32:
946946
; RV64I: # %bb.0:
947-
; RV64I-NEXT: slli a0, a0, 48
948-
; RV64I-NEXT: srli a0, a0, 48
947+
; RV64I-NEXT: lui a1, 16
948+
; RV64I-NEXT: addiw a1, a1, -1
949+
; RV64I-NEXT: and a0, a0, a1
949950
; RV64I-NEXT: ret
950951
;
951952
; RV64ZBB-LABEL: zexth_i32:
952953
; RV64ZBB: # %bb.0:
953-
; RV64ZBB-NEXT: zext.h a0, a0
954+
; RV64ZBB-NEXT: lui a1, 16
955+
; RV64ZBB-NEXT: addiw a1, a1, -1
956+
; RV64ZBB-NEXT: and a0, a0, a1
954957
; RV64ZBB-NEXT: ret
955958
%and = and i32 %a, 65535
956959
ret i32 %and

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