[AArch64] Scalarize i128 add/sub/mul/and/or/xor vectors

This mirrors what we do for SDAG, scalarizing i128 vectors with
add/sub/mul/and/or/xor operators.

Author: davemgreen

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -149,6 +149,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
             return Query.Types[0].getNumElements() <= 16;
           },
           0, s8)
+      .scalarizeIf(scalarOrEltWiderThan(0, 64), 0)
       .moreElementsToNextPow2(0);
 
   getActionDefinitionsBuilder({G_SHL, G_ASHR, G_LSHR})

llvm/test/CodeGen/AArch64/add.ll

@@ -1,10 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc -mtriple=aarch64-none-eabi -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc -mtriple=aarch64-none-eabi -global-isel -global-isel-abort=2 -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-; CHECK-GI:       warning: Instruction selection used fallback path for v2i128
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for v3i128
-; CHECK-GI-NEXT:  warning: Instruction selection used fallback path for v4i128
+; RUN: llc -mtriple=aarch64-none-eabi -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
 
 define i8 @i8(i8 %a, i8 %b) {
 ; CHECK-LABEL: i8:
@@ -480,21 +476,37 @@ entry:
 }
 
 define <4 x i128> @v4i128(<4 x i128> %d, <4 x i128> %e) {
-; CHECK-LABEL: v4i128:
-; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    ldp x8, x9, [sp]
-; CHECK-NEXT:    ldp x11, x10, [sp, #16]
-; CHECK-NEXT:    ldp x13, x12, [sp, #32]
-; CHECK-NEXT:    adds x0, x0, x8
-; CHECK-NEXT:    adc x1, x1, x9
-; CHECK-NEXT:    ldp x8, x9, [sp, #48]
-; CHECK-NEXT:    adds x2, x2, x11
-; CHECK-NEXT:    adc x3, x3, x10
-; CHECK-NEXT:    adds x4, x4, x13
-; CHECK-NEXT:    adc x5, x5, x12
-; CHECK-NEXT:    adds x6, x6, x8
-; CHECK-NEXT:    adc x7, x7, x9
-; CHECK-NEXT:    ret
+; CHECK-SD-LABEL: v4i128:
+; CHECK-SD:       // %bb.0: // %entry
+; CHECK-SD-NEXT:    ldp x8, x9, [sp]
+; CHECK-SD-NEXT:    ldp x11, x10, [sp, #16]
+; CHECK-SD-NEXT:    ldp x13, x12, [sp, #32]
+; CHECK-SD-NEXT:    adds x0, x0, x8
+; CHECK-SD-NEXT:    adc x1, x1, x9
+; CHECK-SD-NEXT:    ldp x8, x9, [sp, #48]
+; CHECK-SD-NEXT:    adds x2, x2, x11
+; CHECK-SD-NEXT:    adc x3, x3, x10
+; CHECK-SD-NEXT:    adds x4, x4, x13
+; CHECK-SD-NEXT:    adc x5, x5, x12
+; CHECK-SD-NEXT:    adds x6, x6, x8
+; CHECK-SD-NEXT:    adc x7, x7, x9
+; CHECK-SD-NEXT:    ret
+;
+; CHECK-GI-LABEL: v4i128:
+; CHECK-GI:       // %bb.0: // %entry
+; CHECK-GI-NEXT:    ldp x8, x9, [sp]
+; CHECK-GI-NEXT:    ldp x10, x11, [sp, #16]
+; CHECK-GI-NEXT:    ldp x12, x13, [sp, #32]
+; CHECK-GI-NEXT:    adds x0, x0, x8
+; CHECK-GI-NEXT:    adc x1, x1, x9
+; CHECK-GI-NEXT:    ldp x8, x9, [sp, #48]
+; CHECK-GI-NEXT:    adds x2, x2, x10
+; CHECK-GI-NEXT:    adc x3, x3, x11
+; CHECK-GI-NEXT:    adds x4, x4, x12
+; CHECK-GI-NEXT:    adc x5, x5, x13
+; CHECK-GI-NEXT:    adds x6, x6, x8
+; CHECK-GI-NEXT:    adc x7, x7, x9
+; CHECK-GI-NEXT:    ret
 entry:
   %s = add <4 x i128> %d, %e
   ret <4 x i128> %s