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[RISCV] Add rv64zbkb.ll test for -riscv-experimental-rv64-legal-i32. NFC
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‎llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbkb.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s -check-prefix=RV64I
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \
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; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s -check-prefix=RV64ZBKB
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define signext i32 @pack_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: pack_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: slliw a1, a1, 16
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: slli a0, a0, 48
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; RV64ZBKB-NEXT: srli a0, a0, 48
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; RV64ZBKB-NEXT: slliw a1, a1, 16
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; RV64ZBKB-NEXT: or a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%shl = and i32 %a, 65535
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%shl1 = shl i32 %b, 16
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%or = or i32 %shl1, %shl
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ret i32 %or
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}
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define signext i32 @pack_i32_2(i16 zeroext %a, i16 zeroext %b) nounwind {
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; RV64I-LABEL: pack_i32_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slliw a1, a1, 16
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: slliw a1, a1, 16
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; RV64ZBKB-NEXT: or a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%zexta = zext i16 %a to i32
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%zextb = zext i16 %b to i32
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%shl1 = shl i32 %zextb, 16
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%or = or i32 %shl1, %zexta
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ret i32 %or
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}
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; Test case where we don't have a sign_extend_inreg after the or.
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define signext i32 @pack_i32_3(i16 zeroext %0, i16 zeroext %1, i32 signext %2) {
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; RV64I-LABEL: pack_i32_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 16
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: addw a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_3:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: slli a0, a0, 16
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; RV64ZBKB-NEXT: or a0, a0, a1
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; RV64ZBKB-NEXT: addw a0, a0, a2
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; RV64ZBKB-NEXT: ret
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%4 = zext i16 %0 to i32
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%5 = shl nuw i32 %4, 16
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%6 = zext i16 %1 to i32
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%7 = or i32 %5, %6
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%8 = add i32 %7, %2
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ret i32 %8
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}
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define i64 @pack_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: pack_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: pack a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%shl = and i64 %a, 4294967295
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%shl1 = shl i64 %b, 32
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%or = or i64 %shl1, %shl
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ret i64 %or
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}
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define i64 @pack_i64_2(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: pack_i64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: slli a1, a1, 32
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: pack a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%zexta = zext i32 %a to i64
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%zextb = zext i32 %b to i64
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%shl1 = shl i64 %zextb, 32
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%or = or i64 %shl1, %zexta
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ret i64 %or
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}
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define i64 @pack_i64_3(ptr %0, ptr %1) {
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; RV64I-LABEL: pack_i64_3:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lw a0, 0(a0)
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; RV64I-NEXT: lwu a1, 0(a1)
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: or a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_3:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: lw a0, 0(a0)
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; RV64ZBKB-NEXT: lwu a1, 0(a1)
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; RV64ZBKB-NEXT: pack a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%3 = load i32, ptr %0, align 4
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%4 = zext i32 %3 to i64
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%5 = shl i64 %4, 32
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%6 = load i32, ptr %1, align 4
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%7 = zext i32 %6 to i64
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%8 = or i64 %5, %7
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ret i64 %8
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}
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define signext i32 @packh_i32(i32 signext %a, i32 signext %b) nounwind {
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; RV64I-LABEL: packh_i32:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: andi a0, a0, 255
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; RV64ZBKB-NEXT: slli a1, a1, 56
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; RV64ZBKB-NEXT: srli a1, a1, 48
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; RV64ZBKB-NEXT: or a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = shl i32 %b, 8
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%shl = and i32 %and1, 65280
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i32 @packh_i32_2(i32 %a, i32 %b) nounwind {
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; RV64I-LABEL: packh_i32_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: slliw a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i32_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: andi a0, a0, 255
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; RV64ZBKB-NEXT: andi a1, a1, 255
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; RV64ZBKB-NEXT: slliw a1, a1, 8
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; RV64ZBKB-NEXT: or a0, a1, a0
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; RV64ZBKB-NEXT: ret
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%and = and i32 %a, 255
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%and1 = and i32 %b, 255
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%shl = shl i32 %and1, 8
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%or = or i32 %shl, %and
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ret i32 %or
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}
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define i64 @packh_i64(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: slli a1, a1, 56
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; RV64I-NEXT: srli a1, a1, 48
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = shl i64 %b, 8
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%shl = and i64 %and1, 65280
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define i64 @packh_i64_2(i64 %a, i64 %b) nounwind {
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; RV64I-LABEL: packh_i64_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: andi a0, a0, 255
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; RV64I-NEXT: andi a1, a1, 255
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i64_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: packh a0, a0, a1
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; RV64ZBKB-NEXT: ret
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%and = and i64 %a, 255
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%and1 = and i64 %b, 255
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%shl = shl i64 %and1, 8
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%or = or i64 %shl, %and
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ret i64 %or
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}
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define zeroext i16 @packh_i16(i8 zeroext %a, i8 zeroext %b) nounwind {
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; RV64I-LABEL: packh_i16:
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; RV64I: # %bb.0:
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; RV64I-NEXT: slli a1, a1, 8
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; RV64I-NEXT: or a0, a1, a0
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: srli a0, a0, 32
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i16:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: slli a1, a1, 8
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; RV64ZBKB-NEXT: or a0, a1, a0
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; RV64ZBKB-NEXT: slli a0, a0, 32
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; RV64ZBKB-NEXT: srli a0, a0, 32
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; RV64ZBKB-NEXT: ret
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%zext = zext i8 %a to i16
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%zext1 = zext i8 %b to i16
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%shl = shl i16 %zext1, 8
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%or = or i16 %shl, %zext
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ret i16 %or
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}
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define zeroext i16 @packh_i16_2(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2) {
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; RV64I-LABEL: packh_i16_2:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slli a0, a0, 8
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: slli a0, a0, 48
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; RV64I-NEXT: srli a0, a0, 48
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: packh_i16_2:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: slli a0, a0, 8
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; RV64ZBKB-NEXT: or a0, a0, a2
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; RV64ZBKB-NEXT: slli a0, a0, 48
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; RV64ZBKB-NEXT: srli a0, a0, 48
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; RV64ZBKB-NEXT: ret
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%4 = add i8 %1, %0
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%5 = zext i8 %4 to i16
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%6 = shl i16 %5, 8
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%7 = zext i8 %2 to i16
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%8 = or i16 %6, %7
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ret i16 %8
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}
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define i64 @pack_i64_allWUsers(i32 signext %0, i32 signext %1, i32 signext %2) {
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; RV64I-LABEL: pack_i64_allWUsers:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slli a0, a0, 32
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; RV64I-NEXT: slli a2, a2, 32
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; RV64I-NEXT: srli a2, a2, 32
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_allWUsers:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: pack a0, a2, a0
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; RV64ZBKB-NEXT: ret
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%4 = add i32 %1, %0
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%5 = zext i32 %4 to i64
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%6 = shl i64 %5, 32
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%7 = zext i32 %2 to i64
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%8 = or i64 %6, %7
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ret i64 %8
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}
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define signext i32 @pack_i32_allWUsers(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2) {
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; RV64I-LABEL: pack_i32_allWUsers:
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; RV64I: # %bb.0:
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; RV64I-NEXT: add a0, a1, a0
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; RV64I-NEXT: slliw a0, a0, 16
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; RV64I-NEXT: or a0, a0, a2
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i32_allWUsers:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: add a0, a1, a0
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; RV64ZBKB-NEXT: slliw a0, a0, 16
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; RV64ZBKB-NEXT: or a0, a0, a2
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; RV64ZBKB-NEXT: ret
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%4 = add i16 %1, %0
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%5 = zext i16 %4 to i32
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%6 = shl i32 %5, 16
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%7 = zext i16 %2 to i32
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%8 = or i32 %6, %7
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ret i32 %8
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}
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define i64 @pack_i64_imm() {
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; RV64I-LABEL: pack_i64_imm:
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; RV64I: # %bb.0:
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; RV64I-NEXT: lui a0, 65793
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; RV64I-NEXT: addiw a0, a0, 16
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; RV64I-NEXT: slli a1, a0, 32
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; RV64I-NEXT: add a0, a0, a1
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; RV64I-NEXT: ret
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;
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; RV64ZBKB-LABEL: pack_i64_imm:
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; RV64ZBKB: # %bb.0:
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; RV64ZBKB-NEXT: lui a0, 65793
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; RV64ZBKB-NEXT: addi a0, a0, 16
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; RV64ZBKB-NEXT: pack a0, a0, a0
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; RV64ZBKB-NEXT: ret
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ret i64 1157442765409226768 ; 0x0101010101010101
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}

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