@@ -42,7 +42,7 @@ using namespace lld::elf;
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uint32_t OutputSection::getPhdrFlags () const {
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uint32_t ret = 0 ;
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- if (config-> emachine != EM_ARM || !(flags & SHF_ARM_PURECODE))
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+ if (ctx. arg . emachine != EM_ARM || !(flags & SHF_ARM_PURECODE))
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ret |= PF_R;
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if (flags & SHF_WRITE)
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ret |= PF_W;
@@ -82,7 +82,7 @@ static bool canMergeToProgbits(unsigned type) {
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return type == SHT_NOBITS || type == SHT_PROGBITS || type == SHT_INIT_ARRAY ||
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type == SHT_PREINIT_ARRAY || type == SHT_FINI_ARRAY ||
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type == SHT_NOTE ||
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- (type == SHT_X86_64_UNWIND && config-> emachine == EM_X86_64);
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+ (type == SHT_X86_64_UNWIND && ctx. arg . emachine == EM_X86_64);
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}
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// Record that isec will be placed in the OutputSection. isec does not become
@@ -130,9 +130,9 @@ void OutputSection::commitSection(InputSection *isec) {
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if (type != SHT_NOBITS) {
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errorOrWarn (" section type mismatch for " + isec->name + " \n >>> " +
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toString (isec) + " : " +
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- getELFSectionTypeName (config-> emachine , isec->type ) +
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+ getELFSectionTypeName (ctx. arg . emachine , isec->type ) +
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" \n >>> output section " + name + " : " +
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- getELFSectionTypeName (config-> emachine , type));
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+ getELFSectionTypeName (ctx. arg . emachine , type));
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}
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}
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if (!typeIsSet)
@@ -155,7 +155,7 @@ void OutputSection::commitSection(InputSection *isec) {
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isec->parent = this ;
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uint64_t andMask =
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- config-> emachine == EM_ARM ? (uint64_t )SHF_ARM_PURECODE : 0 ;
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+ ctx. arg . emachine == EM_ARM ? (uint64_t )SHF_ARM_PURECODE : 0 ;
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uint64_t orMask = ~andMask;
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uint64_t andFlags = (flags & isec->flags ) & andMask;
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uint64_t orFlags = (flags | isec->flags ) & orMask;
@@ -176,7 +176,7 @@ static MergeSyntheticSection *createMergeSynthetic(StringRef name,
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uint32_t type,
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uint64_t flags,
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uint32_t addralign) {
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- if ((flags & SHF_STRINGS) && config-> optimize >= 2 )
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+ if ((flags & SHF_STRINGS) && ctx. arg . optimize >= 2 )
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return make<MergeTailSection>(name, type, flags, addralign);
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return make<MergeNoTailSection>(name, type, flags, addralign);
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}
@@ -261,7 +261,7 @@ static void sortByOrder(MutableArrayRef<InputSection *> in,
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}
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uint64_t elf::getHeaderSize () {
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- if (config-> oFormatBinary )
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+ if (ctx. arg . oFormatBinary )
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return 0 ;
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return ctx.out .elfHeader ->size + ctx.out .programHeaders ->size ;
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}
@@ -348,10 +348,10 @@ template <class ELFT> void OutputSection::maybeCompress() {
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DebugCompressionType ctype = DebugCompressionType::None;
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size_t compressedSize = sizeof (Elf_Chdr);
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unsigned level = 0 ; // default compression level
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- if (!(flags & SHF_ALLOC) && config-> compressDebugSections &&
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+ if (!(flags & SHF_ALLOC) && ctx. arg . compressDebugSections &&
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name.starts_with (" .debug_" ))
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- ctype = *config-> compressDebugSections ;
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- for (auto &[glob, t, l] : config-> compressSections )
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+ ctype = *ctx. arg . compressDebugSections ;
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+ for (auto &[glob, t, l] : ctx. arg . compressSections )
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if (glob.match (name))
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std::tie (ctype, level) = {t, l};
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if (ctype == DebugCompressionType::None)
@@ -529,7 +529,7 @@ void OutputSection::writeTo(uint8_t *buf, parallel::TaskGroup &tg) {
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// When in Arm BE8 mode, the linker has to convert the big-endian
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// instructions to little-endian, leaving the data big-endian.
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- if (config-> emachine == EM_ARM && !config-> isLE && config-> armBe8 &&
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+ if (ctx. arg . emachine == EM_ARM && !ctx. arg . isLE && ctx. arg . armBe8 &&
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(flags & SHF_EXECINSTR))
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convertArmInstructionstoBE8 (isec, buf + isec->outSecOff );
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@@ -661,7 +661,7 @@ static size_t relToCrel(raw_svector_ostream &os, Elf_Crel<ELFT::Is64Bits> &out,
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for (auto rel : rels) {
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encodeOneCrel<typename ELFT::uint>(
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os, out, sec->getVA (rel.r_offset ), file.getRelocTargetSym (rel),
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- rel.getType (config-> isMips64EL ), getAddend<ELFT>(rel));
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+ rel.getType (ctx. arg . isMips64EL ), getAddend<ELFT>(rel));
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}
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return rels.size ();
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}
@@ -690,10 +690,10 @@ template <bool is64> void OutputSection::finalizeNonAllocCrel() {
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// Convert REL[A] to CREL.
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if constexpr (is64) {
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- totalCount += config-> isLE ? relToCrel<ELF64LE>(os, out, relSec, sec)
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+ totalCount += ctx. arg . isLE ? relToCrel<ELF64LE>(os, out, relSec, sec)
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: relToCrel<ELF64BE>(os, out, relSec, sec);
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} else {
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- totalCount += config-> isLE ? relToCrel<ELF32LE>(os, out, relSec, sec)
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+ totalCount += ctx. arg . isLE ? relToCrel<ELF32LE>(os, out, relSec, sec)
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: relToCrel<ELF32BE>(os, out, relSec, sec);
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}
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}
@@ -722,7 +722,7 @@ void OutputSection::finalize() {
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return ;
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}
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- if (!config-> copyRelocs || !isStaticRelSecType (type))
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+ if (!ctx. arg . copyRelocs || !isStaticRelSecType (type))
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return ;
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// Skip if 'first' is synthetic, i.e. not a section created by --emit-relocs.
@@ -740,7 +740,7 @@ void OutputSection::finalize() {
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flags |= SHF_INFO_LINK;
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// Finalize the content of non-alloc CREL.
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if (type == SHT_CREL) {
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- if (config-> is64 )
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+ if (ctx. arg . is64 )
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finalizeNonAllocCrel<true >();
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else
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finalizeNonAllocCrel<false >();
@@ -863,7 +863,7 @@ std::array<uint8_t, 4> OutputSection::getFiller() {
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}
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void OutputSection::checkDynRelAddends (const uint8_t *bufStart) {
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- assert (config-> writeAddends && config-> checkDynamicRelocs );
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+ assert (ctx. arg . writeAddends && ctx. arg . checkDynamicRelocs );
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assert (isStaticRelSecType (type));
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SmallVector<InputSection *, 0 > storage;
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ArrayRef<InputSection *> sections = getInputSections (*this , storage);
@@ -881,7 +881,7 @@ void OutputSection::checkDynRelAddends(const uint8_t *bufStart) {
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assert (relOsec != nullptr && " missing output section for relocation" );
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// Some targets have NOBITS synthetic sections with dynamic relocations
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// with non-zero addends. Skip such sections.
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- if (is_contained ({EM_PPC, EM_PPC64}, config-> emachine ) &&
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+ if (is_contained ({EM_PPC, EM_PPC64}, ctx. arg . emachine ) &&
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(rel.inputSec == ctx.in .ppc64LongBranchTarget .get () ||
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rel.inputSec == ctx.in .igotPlt .get ()))
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continue ;
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