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[TableGen] Fix ordering of register classes. (llvm#67245)
This commit: TableGen: Try to fix expensive checks failures d2a9b87 fixed one of the sort() calls, but there's another. Caught on expensive-checks buildbots that started to fail sporadically after submitting [AMDGPU] Add True16 register classes. 469b3bf
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llvm/utils/TableGen/CodeGenRegisters.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1036,8 +1036,8 @@ void CodeGenRegisterClass::computeSubClasses(CodeGenRegBank &RegBank) {
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std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>>
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CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
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CodeGenRegBank &RegBank, const CodeGenSubRegIndex *SubIdx) const {
1039-
auto SizeOrder = [this](const CodeGenRegisterClass *A,
1040-
const CodeGenRegisterClass *B) {
1039+
auto WeakSizeOrder = [this](const CodeGenRegisterClass *A,
1040+
const CodeGenRegisterClass *B) {
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// If there are multiple, identical register classes, prefer the original
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// register class.
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if (A == B)
@@ -1059,7 +1059,7 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
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for (auto &RC : RegClasses)
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if (SuperRegRCsBV[RC.EnumValue])
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SuperRegRCs.emplace_back(&RC);
1062-
llvm::stable_sort(SuperRegRCs, SizeOrder);
1062+
llvm::stable_sort(SuperRegRCs, WeakSizeOrder);
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assert(SuperRegRCs.front() == BiggestSuperRegRC &&
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"Biggest class wasn't first");
@@ -1072,11 +1072,11 @@ CodeGenRegisterClass::getMatchingSubClassWithSubRegs(
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if (SuperRegClassesBV.any())
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SuperRegClasses.push_back(std::make_pair(&RC, SuperRegClassesBV));
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}
1075-
llvm::sort(SuperRegClasses,
1076-
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1077-
const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1078-
return SizeOrder(A.first, B.first);
1079-
});
1075+
llvm::stable_sort(SuperRegClasses,
1076+
[&](const std::pair<CodeGenRegisterClass *, BitVector> &A,
1077+
const std::pair<CodeGenRegisterClass *, BitVector> &B) {
1078+
return WeakSizeOrder(A.first, B.first);
1079+
});
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// Find the biggest subclass and subreg class such that R:subidx is in the
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// subreg class for all R in subclass.

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