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Merged main:3d7802d2107f into amd-gfx:3573343a8b3e
Local branch amd-gfx 3573343 Merged main:202de4a5c6ed into amd-gfx:63f08b5fd01a Remote branch main 3d7802d [Clang] Actually fix tests for __builtin_vectorelements (llvm#69589)
2 parents 3573343 + 3d7802d commit 8ae8308

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21 files changed

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-212
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21 files changed

+1518
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lines changed

‎clang/include/clang/Basic/arm_sve.td

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1871,6 +1871,15 @@ def SVPSEL_COUNT_ALIAS_B : SInst<"svpsel_lane_c8", "}}Pm", "Pc", MergeNone, "",
18711871
def SVPSEL_COUNT_ALIAS_H : SInst<"svpsel_lane_c16", "}}Pm", "Ps", MergeNone, "", [], []>;
18721872
def SVPSEL_COUNT_ALIAS_S : SInst<"svpsel_lane_c32", "}}Pm", "Pi", MergeNone, "", [], []>;
18731873
def SVPSEL_COUNT_ALIAS_D : SInst<"svpsel_lane_c64", "}}Pm", "Pl", MergeNone, "", [], []>;
1874+
1875+
def SVWHILEGE_COUNT : SInst<"svwhilege_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilege_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1876+
def SVWHILEGT_COUNT : SInst<"svwhilegt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilegt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1877+
def SVWHILELE_COUNT : SInst<"svwhilele_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilele_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1878+
def SVWHILELT_COUNT : SInst<"svwhilelt_{d}", "}lli", "QcQsQiQl", MergeNone, "aarch64_sve_whilelt_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1879+
def SVWHILELO_COUNT : SInst<"svwhilelo_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilelo_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1880+
def SVWHILELS_COUNT : SInst<"svwhilels_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilels_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1881+
def SVWHILEHI_COUNT : SInst<"svwhilehi_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehi_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
1882+
def SVWHILEHS_COUNT : SInst<"svwhilehs_{d}", "}nni", "QcQsQiQl", MergeNone, "aarch64_sve_whilehs_{d}", [IsOverloadNone], [ImmCheck<2, ImmCheck2_4_Mul2>]>;
18741883
}
18751884

18761885
let TargetGuard = "sve2p1" in {

‎clang/lib/AST/Interp/IntegralAP.h

Lines changed: 62 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,9 @@ template <unsigned Bits, bool Signed> class Integral;
3333
template <bool Signed> class IntegralAP final {
3434
private:
3535
friend IntegralAP<!Signed>;
36-
APSInt V;
36+
APInt V;
3737

38-
template <typename T> static T truncateCast(const APSInt &V) {
38+
template <typename T> static T truncateCast(const APInt &V) {
3939
constexpr unsigned BitSize = sizeof(T) * 8;
4040
if (BitSize >= V.getBitWidth())
4141
return std::is_signed_v<T> ? V.getSExtValue() : V.getZExtValue();
@@ -48,23 +48,37 @@ template <bool Signed> class IntegralAP final {
4848
using AsUnsigned = IntegralAP<false>;
4949

5050
template <typename T>
51-
IntegralAP(T Value)
52-
: V(APInt(sizeof(T) * 8, static_cast<uint64_t>(Value),
53-
std::is_signed_v<T>)) {}
51+
IntegralAP(T Value, unsigned BitWidth)
52+
: V(APInt(BitWidth, static_cast<uint64_t>(Value), Signed)) {}
5453

5554
IntegralAP(APInt V) : V(V) {}
56-
IntegralAP(APSInt V) : V(V) {}
5755
/// Arbitrary value for uninitialized variables.
58-
IntegralAP() : V(APSInt::getMaxValue(1024, Signed)) {}
56+
IntegralAP() : IntegralAP(-1, 1024) {}
5957

6058
IntegralAP operator-() const { return IntegralAP(-V); }
6159
IntegralAP operator-(const IntegralAP &Other) const {
6260
return IntegralAP(V - Other.V);
6361
}
64-
bool operator>(IntegralAP RHS) const { return V > RHS.V; }
65-
bool operator>=(IntegralAP RHS) const { return V >= RHS.V; }
66-
bool operator<(IntegralAP RHS) const { return V < RHS.V; }
67-
bool operator<=(IntegralAP RHS) const { return V <= RHS.V; }
62+
bool operator>(const IntegralAP &RHS) const {
63+
if constexpr (Signed)
64+
return V.ugt(RHS.V);
65+
return V.sgt(RHS.V);
66+
}
67+
bool operator>=(IntegralAP RHS) const {
68+
if constexpr (Signed)
69+
return V.uge(RHS.V);
70+
return V.sge(RHS.V);
71+
}
72+
bool operator<(IntegralAP RHS) const {
73+
if constexpr (Signed)
74+
return V.slt(RHS.V);
75+
return V.slt(RHS.V);
76+
}
77+
bool operator<=(IntegralAP RHS) const {
78+
if constexpr (Signed)
79+
return V.ult(RHS.V);
80+
return V.ult(RHS.V);
81+
}
6882

6983
explicit operator bool() const { return !V.isZero(); }
7084
explicit operator int8_t() const { return truncateCast<int8_t>(V); }
@@ -78,42 +92,32 @@ template <bool Signed> class IntegralAP final {
7892

7993
template <typename T> static IntegralAP from(T Value, unsigned NumBits = 0) {
8094
assert(NumBits > 0);
81-
APSInt Copy =
82-
APSInt(APInt(NumBits, static_cast<uint64_t>(Value), Signed), !Signed);
95+
APInt Copy = APInt(NumBits, static_cast<uint64_t>(Value), Signed);
8396

8497
return IntegralAP<Signed>(Copy);
8598
}
8699

87100
template <bool InputSigned>
88101
static IntegralAP from(IntegralAP<InputSigned> V, unsigned NumBits = 0) {
89-
if constexpr (Signed == InputSigned)
90-
return V;
91-
92-
APSInt Copy = V.V;
93-
Copy.setIsSigned(Signed);
94-
95-
return IntegralAP<Signed>(Copy);
102+
return IntegralAP<Signed>(V.V);
96103
}
97104

98105
template <unsigned Bits, bool InputSigned>
99106
static IntegralAP from(Integral<Bits, InputSigned> I, unsigned BitWidth) {
100-
APSInt Copy =
101-
APSInt(APInt(BitWidth, static_cast<uint64_t>(I), InputSigned), !Signed);
102-
Copy.setIsSigned(Signed);
107+
APInt Copy = APInt(BitWidth, static_cast<uint64_t>(I), InputSigned);
103108

104-
assert(Copy.isSigned() == Signed);
105109
return IntegralAP<Signed>(Copy);
106110
}
107111

108112
static IntegralAP zero(int32_t BitWidth) {
109-
APSInt V = APSInt(APInt(BitWidth, 0LL, Signed), !Signed);
113+
APInt V = APInt(BitWidth, 0LL, Signed);
110114
return IntegralAP(V);
111115
}
112116

113117
constexpr unsigned bitWidth() const { return V.getBitWidth(); }
114118

115-
APSInt toAPSInt(unsigned Bits = 0) const { return V; }
116-
APValue toAPValue() const { return APValue(V); }
119+
APSInt toAPSInt(unsigned Bits = 0) const { return APSInt(V, Signed); }
120+
APValue toAPValue() const { return APValue(APSInt(V, Signed)); }
117121

118122
bool isZero() const { return V.isZero(); }
119123
bool isPositive() const { return V.isNonNegative(); }
@@ -139,22 +143,38 @@ template <bool Signed> class IntegralAP final {
139143
}
140144

141145
IntegralAP<false> toUnsigned() const {
142-
APSInt Copy = V;
143-
Copy.setIsSigned(false);
146+
APInt Copy = V;
144147
return IntegralAP<false>(Copy);
145148
}
146149

147150
ComparisonCategoryResult compare(const IntegralAP &RHS) const {
148-
return Compare(V, RHS.V);
151+
assert(Signed == RHS.isSigned());
152+
assert(bitWidth() == RHS.bitWidth());
153+
if constexpr (Signed) {
154+
if (V.slt(RHS.V))
155+
return ComparisonCategoryResult::Less;
156+
if (V.sgt(RHS.V))
157+
return ComparisonCategoryResult::Greater;
158+
return ComparisonCategoryResult::Equal;
159+
}
160+
161+
assert(!Signed);
162+
if (V.ult(RHS.V))
163+
return ComparisonCategoryResult::Less;
164+
if (V.ugt(RHS.V))
165+
return ComparisonCategoryResult::Greater;
166+
return ComparisonCategoryResult::Equal;
149167
}
150168

151169
static bool increment(IntegralAP A, IntegralAP *R) {
170+
// FIXME: Implement.
152171
assert(false);
153-
*R = IntegralAP(A.V + 1);
172+
*R = IntegralAP(A.V - 1);
154173
return false;
155174
}
156175

157176
static bool decrement(IntegralAP A, IntegralAP *R) {
177+
// FIXME: Implement.
158178
assert(false);
159179
*R = IntegralAP(A.V - 1);
160180
return false;
@@ -170,48 +190,46 @@ template <bool Signed> class IntegralAP final {
170190
}
171191

172192
static bool mul(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
193+
// FIXME: Implement.
173194
assert(false);
174-
// return CheckMulUB(A.V, B.V, R->V);
175195
return false;
176196
}
177197

178198
static bool rem(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
199+
// FIXME: Implement.
179200
assert(false);
180-
*R = IntegralAP(A.V % B.V);
181201
return false;
182202
}
183203

184204
static bool div(IntegralAP A, IntegralAP B, unsigned OpBits, IntegralAP *R) {
205+
// FIXME: Implement.
185206
assert(false);
186-
*R = IntegralAP(A.V / B.V);
187207
return false;
188208
}
189209

190210
static bool bitAnd(IntegralAP A, IntegralAP B, unsigned OpBits,
191211
IntegralAP *R) {
212+
// FIXME: Implement.
192213
assert(false);
193-
*R = IntegralAP(A.V & B.V);
194214
return false;
195215
}
196216

197217
static bool bitOr(IntegralAP A, IntegralAP B, unsigned OpBits,
198218
IntegralAP *R) {
199219
assert(false);
200-
*R = IntegralAP(A.V | B.V);
201220
return false;
202221
}
203222

204223
static bool bitXor(IntegralAP A, IntegralAP B, unsigned OpBits,
205224
IntegralAP *R) {
225+
// FIXME: Implement.
206226
assert(false);
207-
*R = IntegralAP(A.V ^ B.V);
208227
return false;
209228
}
210229

211230
static bool neg(const IntegralAP &A, IntegralAP *R) {
212-
APSInt AI = A.V;
213-
214-
AI.setIsSigned(Signed);
231+
APInt AI = A.V;
232+
AI.negate();
215233
*R = IntegralAP(AI);
216234
return false;
217235
}
@@ -223,12 +241,12 @@ template <bool Signed> class IntegralAP final {
223241

224242
static void shiftLeft(const IntegralAP A, const IntegralAP B, unsigned OpBits,
225243
IntegralAP *R) {
226-
*R = IntegralAP(A.V << B.V.getZExtValue());
244+
*R = IntegralAP(A.V.shl(B.V.getZExtValue()));
227245
}
228246

229247
static void shiftRight(const IntegralAP A, const IntegralAP B,
230248
unsigned OpBits, IntegralAP *R) {
231-
*R = IntegralAP(A.V >> B.V.getZExtValue());
249+
*R = IntegralAP(A.V.ashr(B.V.getZExtValue()));
232250
}
233251

234252
private:
@@ -239,8 +257,8 @@ template <bool Signed> class IntegralAP final {
239257
return false;
240258
}
241259

242-
const APSInt &LHS = A.V;
243-
const APSInt &RHS = B.V;
260+
const APSInt &LHS = APSInt(A.V, A.isSigned());
261+
const APSInt &RHS = APSInt(B.V, B.isSigned());
244262

245263
APSInt Value(LHS.extend(BitWidth) + RHS.extend(BitWidth), false);
246264
APSInt Result = Value.trunc(LHS.getBitWidth());

‎clang/lib/Driver/ToolChains/Arch/ARM.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -627,6 +627,11 @@ llvm::ARM::FPUKind arm::getARMTargetFeatures(const Driver &D,
627627
if (!llvm::ARM::getFPUFeatures(FPUKind, Features))
628628
D.Diag(clang::diag::err_drv_clang_unsupported)
629629
<< std::string("-mfpu=") + AndroidFPU;
630+
} else if (ArchArgFPUKind != llvm::ARM::FK_INVALID ||
631+
CPUArgFPUKind != llvm::ARM::FK_INVALID) {
632+
FPUKind =
633+
CPUArgFPUKind != llvm::ARM::FK_INVALID ? CPUArgFPUKind : ArchArgFPUKind;
634+
(void)llvm::ARM::getFPUFeatures(FPUKind, Features);
630635
} else {
631636
if (!ForAS) {
632637
std::string CPU = arm::getARMTargetCPU(CPUName, ArchName, Triple);

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