Merged main:ea81e31aa11c into amd-gfx:376ca00d5225

Local branch amd-gfx 376ca00 Merged main:28d91a6e17c5 into amd-gfx:ebf5bb705044
Remote branch main ea81e31 [X86][AVX10] Allow AVX10 use VBMI2 instructions (llvm#73276)

Author: SC llvm team

llvm/include/llvm/CodeGen/SelectionDAGISel.h

@@ -124,17 +124,31 @@ class SelectionDAGISel : public MachineFunctionPass {
   enum BuiltinOpcodes {
     OPC_Scope,
     OPC_RecordNode,
-    OPC_RecordChild0, OPC_RecordChild1, OPC_RecordChild2, OPC_RecordChild3,
-    OPC_RecordChild4, OPC_RecordChild5, OPC_RecordChild6, OPC_RecordChild7,
+    OPC_RecordChild0,
+    OPC_RecordChild1,
+    OPC_RecordChild2,
+    OPC_RecordChild3,
+    OPC_RecordChild4,
+    OPC_RecordChild5,
+    OPC_RecordChild6,
+    OPC_RecordChild7,
     OPC_RecordMemRef,
     OPC_CaptureGlueInput,
     OPC_MoveChild,
-    OPC_MoveChild0, OPC_MoveChild1, OPC_MoveChild2, OPC_MoveChild3,
-    OPC_MoveChild4, OPC_MoveChild5, OPC_MoveChild6, OPC_MoveChild7,
+    OPC_MoveChild0,
+    OPC_MoveChild1,
+    OPC_MoveChild2,
+    OPC_MoveChild3,
+    OPC_MoveChild4,
+    OPC_MoveChild5,
+    OPC_MoveChild6,
+    OPC_MoveChild7,
     OPC_MoveParent,
     OPC_CheckSame,
-    OPC_CheckChild0Same, OPC_CheckChild1Same,
-    OPC_CheckChild2Same, OPC_CheckChild3Same,
+    OPC_CheckChild0Same,
+    OPC_CheckChild1Same,
+    OPC_CheckChild2Same,
+    OPC_CheckChild3Same,
     OPC_CheckPatternPredicate,
     OPC_CheckPatternPredicate2,
     OPC_CheckPredicate,
@@ -144,16 +158,26 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_CheckType,
     OPC_CheckTypeRes,
     OPC_SwitchType,
-    OPC_CheckChild0Type, OPC_CheckChild1Type, OPC_CheckChild2Type,
-    OPC_CheckChild3Type, OPC_CheckChild4Type, OPC_CheckChild5Type,
-    OPC_CheckChild6Type, OPC_CheckChild7Type,
+    OPC_CheckChild0Type,
+    OPC_CheckChild1Type,
+    OPC_CheckChild2Type,
+    OPC_CheckChild3Type,
+    OPC_CheckChild4Type,
+    OPC_CheckChild5Type,
+    OPC_CheckChild6Type,
+    OPC_CheckChild7Type,
     OPC_CheckInteger,
-    OPC_CheckChild0Integer, OPC_CheckChild1Integer, OPC_CheckChild2Integer,
-    OPC_CheckChild3Integer, OPC_CheckChild4Integer,
-    OPC_CheckCondCode, OPC_CheckChild2CondCode,
+    OPC_CheckChild0Integer,
+    OPC_CheckChild1Integer,
+    OPC_CheckChild2Integer,
+    OPC_CheckChild3Integer,
+    OPC_CheckChild4Integer,
+    OPC_CheckCondCode,
+    OPC_CheckChild2CondCode,
     OPC_CheckValueType,
     OPC_CheckComplexPat,
-    OPC_CheckAndImm, OPC_CheckOrImm,
+    OPC_CheckAndImm,
+    OPC_CheckOrImm,
     OPC_CheckImmAllOnesV,
     OPC_CheckImmAllZerosV,
     OPC_CheckFoldableChainNode,
@@ -172,10 +196,14 @@ class SelectionDAGISel : public MachineFunctionPass {
     OPC_EmitNodeXForm,
     OPC_EmitNode,
     // Space-optimized forms that implicitly encode number of result VTs.
-    OPC_EmitNode0, OPC_EmitNode1, OPC_EmitNode2,
+    OPC_EmitNode0,
+    OPC_EmitNode1,
+    OPC_EmitNode2,
     OPC_MorphNodeTo,
     // Space-optimized forms that implicitly encode number of result VTs.
-    OPC_MorphNodeTo0, OPC_MorphNodeTo1, OPC_MorphNodeTo2,
+    OPC_MorphNodeTo0,
+    OPC_MorphNodeTo1,
+    OPC_MorphNodeTo2,
     OPC_CompleteMatch,
     // Contains offset in table for pattern being selected
     OPC_Coverage

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 481620
+#define LLVM_MAIN_REVISION 481626
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h

@@ -31,6 +31,7 @@ namespace X86Disassembler {
 #define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
 #define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
 #define THREEDNOW_MAP_SYM x86Disassembler3DNowOpcodes
+#define MAP4_SYM x86DisassemblerMap4Opcodes
 #define MAP5_SYM x86DisassemblerMap5Opcodes
 #define MAP6_SYM x86DisassemblerMap6Opcodes
 #define MAP7_SYM x86DisassemblerMap7Opcodes
@@ -45,6 +46,7 @@ namespace X86Disassembler {
 #define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
 #define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
 #define THREEDNOW_MAP_STR "x86Disassembler3DNowOpcodes"
+#define MAP4_STR "x86DisassemblerMap4Opcodes"
 #define MAP5_STR "x86DisassemblerMap5Opcodes"
 #define MAP6_STR "x86DisassemblerMap6Opcodes"
 #define MAP7_STR "x86DisassemblerMap7Opcodes"
@@ -324,9 +326,10 @@ enum OpcodeType {
   XOP9_MAP = 5,
   XOPA_MAP = 6,
   THREEDNOW_MAP = 7,
-  MAP5 = 8,
-  MAP6 = 9,
-  MAP7 = 10
+  MAP4 = 8,
+  MAP5 = 9,
+  MAP6 = 10,
+  MAP7 = 11
 };
 
 // The following structs are used for the hierarchical decode table.  After

llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

@@ -150,6 +150,9 @@ static InstrUID decode(OpcodeType type, InstructionContext insnContext,
     dec =
         &THREEDNOW_MAP_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
     break;
+  case MAP4:
+    dec = &MAP4_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
+    break;
   case MAP5:
     dec = &MAP5_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
     break;
@@ -929,6 +932,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
     case VEX_LOB_0F3A:
       insn->opcodeType = THREEBYTE_3A;
       return consume(insn, insn->opcode);
+    case VEX_LOB_MAP4:
+      insn->opcodeType = MAP4;
+      return consume(insn, insn->opcode);
     case VEX_LOB_MAP5:
       insn->opcodeType = MAP5;
       return consume(insn, insn->opcode);
@@ -1100,6 +1106,9 @@ static int getInstructionIDWithAttrMask(uint16_t *instructionID,
   case THREEDNOW_MAP:
     decision = &THREEDNOW_MAP_SYM;
     break;
+  case MAP4:
+    decision = &MAP4_SYM;
+    break;
   case MAP5:
     decision = &MAP5_SYM;
     break;

llvm/lib/Target/X86/Disassembler/X86DisassemblerDecoder.h

@@ -628,6 +628,7 @@ enum VEXLeadingOpcodeByte {
   VEX_LOB_0F = 0x1,
   VEX_LOB_0F38 = 0x2,
   VEX_LOB_0F3A = 0x3,
+  VEX_LOB_MAP4 = 0x4,
   VEX_LOB_MAP5 = 0x5,
   VEX_LOB_MAP6 = 0x6,
   VEX_LOB_MAP7 = 0x7