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Merged main:8569465adf5e into amd-gfx:c81d641827d7
Local branch amd-gfx c81d641 Merged main:40671bbdefb6 into amd-gfx:462ca5c3d8c6 Remote branch main 8569465 Add a Clang NATVIS visualizer for StringLiteral
2 parents c81d641 + 8569465 commit 958d879

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16 files changed

+1153
-78
lines changed

16 files changed

+1153
-78
lines changed

‎clang/utils/ClangVisualizers/clang.natvis

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1000,8 +1000,15 @@ For later versions of Visual Studio, no setup is required-->
10001000
</Expand>
10011001
</Type>
10021002
<Type Name="clang::Expr">
1003+
<DisplayString Condition="StmtBits.sClass==clang::Stmt::StmtClass::StringLiteralClass" IncludeView="poly">{*(clang::StringLiteral *)this}</DisplayString>
10031004
<DisplayString>Expression of class {(clang::Stmt::StmtClass)StmtBits.sClass,en} and type {TR,view(cpp)}</DisplayString>
10041005
</Type>
1006+
<Type Name="clang::StringLiteral">
1007+
<Expand>
1008+
<Item Name="Length">*(unsigned *)(((clang::StringLiteral *)this)+1)</Item>
1009+
<Item Name="Data" Condition="StringLiteralBits.NumConcatenated==1">(const char *)(((clang::StringLiteral *)this)+1)+4+4,[*(unsigned *)(((clang::StringLiteral *)this)+1)]s8</Item>
1010+
</Expand>
1011+
</Type>
10051012
<Type Name="clang::DeclAccessPair">
10061013
<DisplayString IncludeView="access" Condition="(Ptr&amp;Mask) == clang::AS_public">public</DisplayString>
10071014
<DisplayString IncludeView="access" Condition="(Ptr&amp;Mask) == clang::AS_protected">protected</DisplayString>

‎llvm/include/llvm/Config/llvm-config.h.cmake

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
/* Indicate that this is LLVM compiled from the amd-gfx branch. */
1818
#define LLVM_HAVE_BRANCH_AMD_GFX
19-
#define LLVM_MAIN_REVISION 480525
19+
#define LLVM_MAIN_REVISION 480529
2020

2121
/* Define if LLVM_ENABLE_DUMP is enabled */
2222
#cmakedefine LLVM_ENABLE_DUMP

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp

Lines changed: 14 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,9 @@ void NVPTXDAGToDAGISel::Select(SDNode *N) {
105105
case NVPTXISD::SETP_F16X2:
106106
SelectSETP_F16X2(N);
107107
return;
108-
108+
case NVPTXISD::SETP_BF16X2:
109+
SelectSETP_BF16X2(N);
110+
return;
109111
case NVPTXISD::LoadV2:
110112
case NVPTXISD::LoadV4:
111113
if (tryLoadVector(N))
@@ -608,6 +610,17 @@ bool NVPTXDAGToDAGISel::SelectSETP_F16X2(SDNode *N) {
608610
return true;
609611
}
610612

613+
bool NVPTXDAGToDAGISel::SelectSETP_BF16X2(SDNode *N) {
614+
unsigned PTXCmpMode =
615+
getPTXCmpMode(*cast<CondCodeSDNode>(N->getOperand(2)), useF32FTZ());
616+
SDLoc DL(N);
617+
SDNode *SetP = CurDAG->getMachineNode(
618+
NVPTX::SETP_bf16x2rr, DL, MVT::i1, MVT::i1, N->getOperand(0),
619+
N->getOperand(1), CurDAG->getTargetConstant(PTXCmpMode, DL, MVT::i32));
620+
ReplaceNode(N, SetP);
621+
return true;
622+
}
623+
611624
// Find all instances of extract_vector_elt that use this v2f16 vector
612625
// and coalesce them into a scattering move instruction.
613626
bool NVPTXDAGToDAGISel::tryEXTRACT_VECTOR_ELEMENT(SDNode *N) {

‎llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@ class LLVM_LIBRARY_VISIBILITY NVPTXDAGToDAGISel : public SelectionDAGISel {
7474
bool tryBFE(SDNode *N);
7575
bool tryConstantFP(SDNode *N);
7676
bool SelectSETP_F16X2(SDNode *N);
77+
bool SelectSETP_BF16X2(SDNode *N);
7778
bool tryEXTRACT_VECTOR_ELEMENT(SDNode *N);
7879

7980
inline SDValue getI32Imm(unsigned Imm, const SDLoc &DL) {

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp

Lines changed: 49 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -436,6 +436,15 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
436436
case ISD::FADD:
437437
case ISD::FMUL:
438438
case ISD::FSUB:
439+
case ISD::SELECT:
440+
case ISD::SELECT_CC:
441+
case ISD::SETCC:
442+
case ISD::FEXP2:
443+
case ISD::FCEIL:
444+
case ISD::FFLOOR:
445+
case ISD::FNEARBYINT:
446+
case ISD::FRINT:
447+
case ISD::FTRUNC:
439448
IsOpSupported = STI.getSmVersion() >= 90 && STI.getPTXVersion() >= 78;
440449
break;
441450
}
@@ -488,8 +497,10 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
488497
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2bf16, Expand);
489498
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2bf16, Expand);
490499

491-
setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote);
492500
setBF16OperationAction(ISD::SETCC, MVT::v2bf16, Legal, Expand);
501+
setBF16OperationAction(ISD::SETCC, MVT::bf16, Legal, Promote);
502+
if (getOperationAction(ISD::SETCC, MVT::bf16) == Promote)
503+
AddPromotedToType(ISD::SETCC, MVT::bf16, MVT::f32);
493504

494505
// Conversion to/from i16/i16x2 is always legal.
495506
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i16, Custom);
@@ -719,9 +730,9 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
719730
for (const auto &Op : {ISD::FADD, ISD::FMUL, ISD::FSUB, ISD::FMA}) {
720731
setFP16OperationAction(Op, MVT::f16, Legal, Promote);
721732
setFP16OperationAction(Op, MVT::v2f16, Legal, Expand);
722-
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
723733
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
724734
// bf16 must be promoted to f32.
735+
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
725736
if (getOperationAction(Op, MVT::bf16) == Promote)
726737
AddPromotedToType(Op, MVT::bf16, MVT::f32);
727738
}
@@ -741,21 +752,23 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
741752
// These map to conversion instructions for scalar FP types.
742753
for (const auto &Op : {ISD::FCEIL, ISD::FFLOOR, ISD::FNEARBYINT, ISD::FRINT,
743754
ISD::FROUNDEVEN, ISD::FTRUNC}) {
744-
setOperationAction(Op, MVT::bf16, Legal);
745755
setOperationAction(Op, MVT::f16, Legal);
746756
setOperationAction(Op, MVT::f32, Legal);
747757
setOperationAction(Op, MVT::f64, Legal);
748758
setOperationAction(Op, MVT::v2f16, Expand);
749759
setOperationAction(Op, MVT::v2bf16, Expand);
760+
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
761+
if (getOperationAction(Op, MVT::bf16) == Promote)
762+
AddPromotedToType(Op, MVT::bf16, MVT::f32);
750763
}
751764

752765
setOperationAction(ISD::FROUND, MVT::f16, Promote);
753766
setOperationAction(ISD::FROUND, MVT::v2f16, Expand);
754-
setOperationAction(ISD::FROUND, MVT::bf16, Promote);
755767
setOperationAction(ISD::FROUND, MVT::v2bf16, Expand);
756768
setOperationAction(ISD::FROUND, MVT::f32, Custom);
757769
setOperationAction(ISD::FROUND, MVT::f64, Custom);
758-
770+
setOperationAction(ISD::FROUND, MVT::bf16, Promote);
771+
AddPromotedToType(ISD::FROUND, MVT::bf16, MVT::f32);
759772

760773
// 'Expand' implements FCOPYSIGN without calling an external library.
761774
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
@@ -769,26 +782,40 @@ NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
769782
// promoted to f32. v2f16 is expanded to f16, which is then promoted
770783
// to f32.
771784
for (const auto &Op :
772-
{ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FABS}) {
785+
{ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS}) {
773786
setOperationAction(Op, MVT::f16, Promote);
774-
setOperationAction(Op, MVT::bf16, Promote);
775787
setOperationAction(Op, MVT::f32, Legal);
776788
setOperationAction(Op, MVT::f64, Legal);
777789
setOperationAction(Op, MVT::v2f16, Expand);
778790
setOperationAction(Op, MVT::v2bf16, Expand);
791+
setOperationAction(Op, MVT::bf16, Promote);
792+
AddPromotedToType(Op, MVT::bf16, MVT::f32);
793+
}
794+
for (const auto &Op : {ISD::FABS}) {
795+
setOperationAction(Op, MVT::f16, Promote);
796+
setOperationAction(Op, MVT::f32, Legal);
797+
setOperationAction(Op, MVT::f64, Legal);
798+
setOperationAction(Op, MVT::v2f16, Expand);
799+
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
800+
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
801+
if (getOperationAction(Op, MVT::bf16) == Promote)
802+
AddPromotedToType(Op, MVT::bf16, MVT::f32);
779803
}
804+
780805
// max.f16, max.f16x2 and max.NaN are supported on sm_80+.
781806
auto GetMinMaxAction = [&](LegalizeAction NotSm80Action) {
782807
bool IsAtLeastSm80 = STI.getSmVersion() >= 80 && STI.getPTXVersion() >= 70;
783808
return IsAtLeastSm80 ? Legal : NotSm80Action;
784809
};
785810
for (const auto &Op : {ISD::FMINNUM, ISD::FMAXNUM}) {
786811
setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Promote), Promote);
787-
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
788812
setOperationAction(Op, MVT::f32, Legal);
789813
setOperationAction(Op, MVT::f64, Legal);
790814
setFP16OperationAction(Op, MVT::v2f16, GetMinMaxAction(Expand), Expand);
791815
setBF16OperationAction(Op, MVT::v2bf16, Legal, Expand);
816+
setBF16OperationAction(Op, MVT::bf16, Legal, Promote);
817+
if (getOperationAction(Op, MVT::bf16) == Promote)
818+
AddPromotedToType(Op, MVT::bf16, MVT::f32);
792819
}
793820
for (const auto &Op : {ISD::FMINIMUM, ISD::FMAXIMUM}) {
794821
setFP16OperationAction(Op, MVT::f16, GetMinMaxAction(Expand), Expand);
@@ -920,6 +947,8 @@ const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
920947
return "NVPTXISD::PRMT";
921948
case NVPTXISD::SETP_F16X2:
922949
return "NVPTXISD::SETP_F16X2";
950+
case NVPTXISD::SETP_BF16X2:
951+
return "NVPTXISD::SETP_BF16X2";
923952
case NVPTXISD::Dummy:
924953
return "NVPTXISD::Dummy";
925954
case NVPTXISD::MUL_WIDE_SIGNED:
@@ -5382,22 +5411,28 @@ static SDValue PerformSHLCombine(SDNode *N,
53825411
}
53835412

53845413
static SDValue PerformSETCCCombine(SDNode *N,
5385-
TargetLowering::DAGCombinerInfo &DCI) {
5414+
TargetLowering::DAGCombinerInfo &DCI,
5415+
unsigned int SmVersion) {
53865416
EVT CCType = N->getValueType(0);
53875417
SDValue A = N->getOperand(0);
53885418
SDValue B = N->getOperand(1);
53895419

5390-
if (CCType != MVT::v2i1 || A.getValueType() != MVT::v2f16)
5420+
EVT AType = A.getValueType();
5421+
if (!(CCType == MVT::v2i1 && (AType == MVT::v2f16 || AType == MVT::v2bf16)))
5422+
return SDValue();
5423+
5424+
if (A.getValueType() == MVT::v2bf16 && SmVersion < 90)
53915425
return SDValue();
53925426

53935427
SDLoc DL(N);
53945428
// setp.f16x2 returns two scalar predicates, which we need to
53955429
// convert back to v2i1. The returned result will be scalarized by
53965430
// the legalizer, but the comparison will remain a single vector
53975431
// instruction.
5398-
SDValue CCNode = DCI.DAG.getNode(NVPTXISD::SETP_F16X2, DL,
5399-
DCI.DAG.getVTList(MVT::i1, MVT::i1),
5400-
{A, B, N->getOperand(2)});
5432+
SDValue CCNode = DCI.DAG.getNode(
5433+
A.getValueType() == MVT::v2f16 ? NVPTXISD::SETP_F16X2
5434+
: NVPTXISD::SETP_BF16X2,
5435+
DL, DCI.DAG.getVTList(MVT::i1, MVT::i1), {A, B, N->getOperand(2)});
54015436
return DCI.DAG.getNode(ISD::BUILD_VECTOR, DL, CCType, CCNode.getValue(0),
54025437
CCNode.getValue(1));
54035438
}
@@ -5536,7 +5571,7 @@ SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
55365571
case ISD::SREM:
55375572
return PerformREMCombine(N, DCI, OptLevel);
55385573
case ISD::SETCC:
5539-
return PerformSETCCCombine(N, DCI);
5574+
return PerformSETCCCombine(N, DCI, STI.getSmVersion());
55405575
case ISD::LOAD:
55415576
return PerformLOADCombine(N, DCI);
55425577
case NVPTXISD::StoreRetval:

‎llvm/lib/Target/NVPTX/NVPTXISelLowering.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ enum NodeType : unsigned {
5757
MUL_WIDE_UNSIGNED,
5858
IMAD,
5959
SETP_F16X2,
60+
SETP_BF16X2,
6061
BFE,
6162
BFI,
6263
PRMT,

‎llvm/lib/Target/NVPTX/NVPTXInstrInfo.td

Lines changed: 34 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -555,6 +555,34 @@ multiclass F2<string OpcStr, SDNode OpNode> {
555555
[(set Float32Regs:$dst, (OpNode Float32Regs:$a))]>;
556556
}
557557

558+
multiclass F2_Support_Half<string OpcStr, SDNode OpNode> {
559+
def bf16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a),
560+
!strconcat(OpcStr, ".bf16 \t$dst, $a;"),
561+
[(set Int16Regs:$dst, (OpNode (bf16 Int16Regs:$a)))]>,
562+
Requires<[hasSM<80>, hasPTX<70>]>;
563+
def bf16x2 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a),
564+
!strconcat(OpcStr, ".v2bf16 \t$dst, $a;"),
565+
[(set Int32Regs:$dst, (OpNode (v2bf16 Int32Regs:$a)))]>,
566+
Requires<[hasSM<80>, hasPTX<70>]>;
567+
def f16_ftz : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a),
568+
!strconcat(OpcStr, ".ftz.f16 \t$dst, $a;"),
569+
[(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a)))]>,
570+
Requires<[hasSM<53>, hasPTX<65>, doF32FTZ]>;
571+
def f16x2_ftz : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a),
572+
!strconcat(OpcStr, ".ftz.f16x2 \t$dst, $a;"),
573+
[(set Int32Regs:$dst, (OpNode (v2f16 Int32Regs:$a)))]>,
574+
Requires<[hasSM<53>, hasPTX<65>, doF32FTZ]>;
575+
def f16 : NVPTXInst<(outs Int16Regs:$dst), (ins Int16Regs:$a),
576+
!strconcat(OpcStr, ".f16 \t$dst, $a;"),
577+
[(set Int16Regs:$dst, (OpNode (f16 Int16Regs:$a)))]>,
578+
Requires<[hasSM<53>, hasPTX<65>]>;
579+
def f16x2 : NVPTXInst<(outs Int32Regs:$dst), (ins Int32Regs:$a),
580+
!strconcat(OpcStr, ".f16x2 \t$dst, $a;"),
581+
[(set Int32Regs:$dst, (OpNode (v2f16 Int32Regs:$a)))]>,
582+
Requires<[hasSM<53>, hasPTX<65>]>;
583+
584+
}
585+
558586
//===----------------------------------------------------------------------===//
559587
// NVPTX Instructions.
560588
//===----------------------------------------------------------------------===//
@@ -1139,6 +1167,9 @@ defm FMAXNAN : F3<"max.NaN", fmaximum>;
11391167

11401168
defm FABS : F2<"abs", fabs>;
11411169
defm FNEG : F2<"neg", fneg>;
1170+
defm FABS_H: F2_Support_Half<"abs", fabs>;
1171+
defm FNEG_H: F2_Support_Half<"neg", fneg>;
1172+
11421173
defm FSQRT : F2<"sqrt.rn", fsqrt>;
11431174

11441175
//
@@ -1936,14 +1967,14 @@ def SETP_bf16rr :
19361967
NVPTXInst<(outs Int1Regs:$dst),
19371968
(ins Int16Regs:$a, Int16Regs:$b, CmpMode:$cmp),
19381969
"setp${cmp:base}${cmp:ftz}.bf16 \t$dst, $a, $b;",
1939-
[]>, Requires<[hasBF16Math]>;
1970+
[]>, Requires<[hasBF16Math, hasPTX<78>, hasSM<90>]>;
19401971

19411972
def SETP_bf16x2rr :
19421973
NVPTXInst<(outs Int1Regs:$p, Int1Regs:$q),
19431974
(ins Int32Regs:$a, Int32Regs:$b, CmpMode:$cmp),
19441975
"setp${cmp:base}${cmp:ftz}.bf16x2 \t$p|$q, $a, $b;",
19451976
[]>,
1946-
Requires<[hasBF16Math]>;
1977+
Requires<[hasBF16Math, hasPTX<78>, hasSM<90>]>;
19471978

19481979

19491980
// FIXME: This doesn't appear to be correct. The "set" mnemonic has the form
@@ -1974,7 +2005,7 @@ defm SET_b64 : SET<"b64", Int64Regs, i64imm>;
19742005
defm SET_s64 : SET<"s64", Int64Regs, i64imm>;
19752006
defm SET_u64 : SET<"u64", Int64Regs, i64imm>;
19762007
defm SET_f16 : SET<"f16", Int16Regs, f16imm>;
1977-
defm SET_bf16 : SET<"bf16", Int16Regs, bf16imm>;
2008+
defm SET_bf16 : SET<"bf16", Int16Regs, bf16imm>, Requires<[hasPTX<78>, hasSM<90>]>;
19782009
defm SET_f32 : SET<"f32", Float32Regs, f32imm>;
19792010
defm SET_f64 : SET<"f64", Float64Regs, f64imm>;
19802011

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -8777,14 +8777,13 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) {
87778777
VPBasicBlock *HeaderVPBB = new VPBasicBlock("vector.body");
87788778
VPBasicBlock *LatchVPBB = new VPBasicBlock("vector.latch");
87798779
VPBlockUtils::insertBlockAfter(LatchVPBB, HeaderVPBB);
8780-
auto *TopRegion = new VPRegionBlock(HeaderVPBB, LatchVPBB, "vector loop");
8781-
VPBlockUtils::insertBlockAfter(TopRegion, Plan->getEntry());
8782-
VPBasicBlock *MiddleVPBB = new VPBasicBlock("middle.block");
8783-
VPBlockUtils::insertBlockAfter(MiddleVPBB, TopRegion);
8780+
Plan->getVectorLoopRegion()->setEntry(HeaderVPBB);
8781+
Plan->getVectorLoopRegion()->setExiting(LatchVPBB);
87848782

87858783
// Don't use getDecisionAndClampRange here, because we don't know the UF
87868784
// so this function is better to be conservative, rather than to split
87878785
// it up into different VPlans.
8786+
// TODO: Consider using getDecisionAndClampRange here to split up VPlans.
87888787
bool IVUpdateMayOverflow = false;
87898788
for (ElementCount VF : Range)
87908789
IVUpdateMayOverflow |= !isIndvarOverflowCheckKnownFalse(&CM, VF);

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -714,6 +714,11 @@ VPlanPtr VPlan::createInitialVPlan(const SCEV *TripCount, ScalarEvolution &SE) {
714714
auto Plan = std::make_unique<VPlan>(Preheader, VecPreheader);
715715
Plan->TripCount =
716716
vputils::getOrCreateVPValueForSCEVExpr(*Plan, TripCount, SE);
717+
// Create empty VPRegionBlock, to be filled during processing later.
718+
auto *TopRegion = new VPRegionBlock("vector loop", false /*isReplicator*/);
719+
VPBlockUtils::insertBlockAfter(TopRegion, VecPreheader);
720+
VPBasicBlock *MiddleVPBB = new VPBasicBlock("middle.block");
721+
VPBlockUtils::insertBlockAfter(MiddleVPBB, TopRegion);
717722
return Plan;
718723
}
719724

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2561,8 +2561,11 @@ class VPlan {
25612561

25622562
~VPlan();
25632563

2564-
/// Create an initial VPlan with preheader and entry blocks. Creates a
2565-
/// VPExpandSCEVRecipe for \p TripCount and uses it as plan's trip count.
2564+
/// Create initial VPlan skeleton, having an "entry" VPBasicBlock (wrapping
2565+
/// original scalar pre-header) which contains SCEV expansions that need to
2566+
/// happen before the CFG is modified; a VPBasicBlock for the vector
2567+
/// pre-header, followed by a region for the vector loop, followed by the
2568+
/// middle VPBasicBlock.
25662569
static VPlanPtr createInitialVPlan(const SCEV *TripCount,
25672570
ScalarEvolution &PSE);
25682571

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