Merged main:5b7982f2b223 into amd-gfx:ee2d08d63842

Local branch amd-gfx ee2d08d Merged main:1438544e2364 into amd-gfx:33cd95d2c4a1
Remote branch main 5b7982f [RISCV] Fix SiFive7 formula for Reductions and ordered Reductions  (llvm#65385)

Author: SC llvm team

libcxx/utils/ci/buildkite-pipeline.yml

@@ -1119,8 +1119,8 @@ steps:
         - "**/test-results.xml"
         - "**/*.abilist"
       env:
-          CC: "clang15"
-          CXX: "clang++15"
+          CC: "clang16"
+          CXX: "clang++16"
           ENABLE_STD_MODULES: "Off"
       agents:
         queue: "libcxx-builders"

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 473676
+#define LLVM_MAIN_REVISION 473678
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -154,12 +154,12 @@ class SiFive7GetReductionCycles<string mx, int sew> {
     !eq(mx, "MF8") : 1
   );
   int c = !add(
-    !div(TwoTimesLMUL, DLEN),
+    TwoTimesLMUL,
     !mul(5, !add(4, !logtwo(!div(DLEN, sew))))
   );
 }
 
-/// Cycles for ordered reductions take approximatley 5*VL cycles
+/// Cycles for ordered reductions take approximatley 6*VL cycles
 class SiFive7GetOrderedReductionCycles<string mx, int sew> {
   defvar VLEN = 512;
   // (VLEN * LMUL) / SEW
@@ -172,7 +172,7 @@ class SiFive7GetOrderedReductionCycles<string mx, int sew> {
     !eq(mx, "MF4") : !div(!div(VLEN, 4), sew),
     !eq(mx, "MF8") : !div(!div(VLEN, 8), sew),
   );
-  int c = !mul(5, VLUpperBound);
+  int c = !mul(6, VLUpperBound);
 }
 
 class SiFive7AnyToGPRBypass<SchedRead read, int cycles = 2>