Skip to content

Commit b51130a

Browse files
RKSimonRKSimon
committed
[X86] combine-fneg.ll - replace X32 checks with X86. NFC.
We try to use X32 for gnux32 triples only.
1 parent 4ecd638 commit b51130a

File tree

1 file changed

+68
-68
lines changed

1 file changed

+68
-68
lines changed

‎llvm/test/CodeGen/X86/combine-fneg.ll

Lines changed: 68 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,17 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE1
3-
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE2
4-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE1
5-
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE2
2+
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse | FileCheck %s --check-prefixes=X86-SSE,X86-SSE1
3+
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86-SSE,X86-SSE2
4+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=-sse2 | FileCheck %s --check-prefixes=X64-SSE,X64-SSE1
5+
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X64-SSE,X64-SSE2
66

77
; FNEG is defined as subtraction from -0.0.
88

99
; This test verifies that we use an xor with a constant to flip the sign bits; no subtraction needed.
1010
define <4 x float> @t1(<4 x float> %Q) nounwind {
11-
; X32-SSE-LABEL: t1:
12-
; X32-SSE: # %bb.0:
13-
; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
14-
; X32-SSE-NEXT: retl
11+
; X86-SSE-LABEL: t1:
12+
; X86-SSE: # %bb.0:
13+
; X86-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
14+
; X86-SSE-NEXT: retl
1515
;
1616
; X64-SSE-LABEL: t1:
1717
; X64-SSE: # %bb.0:
@@ -24,10 +24,10 @@ define <4 x float> @t1(<4 x float> %Q) nounwind {
2424
; Possibly misplaced test, but since we're checking undef scenarios...
2525

2626
define float @scalar_fsub_neg0_undef(float %x) nounwind {
27-
; X32-SSE-LABEL: scalar_fsub_neg0_undef:
28-
; X32-SSE: # %bb.0:
29-
; X32-SSE-NEXT: fldz
30-
; X32-SSE-NEXT: retl
27+
; X86-SSE-LABEL: scalar_fsub_neg0_undef:
28+
; X86-SSE: # %bb.0:
29+
; X86-SSE-NEXT: fldz
30+
; X86-SSE-NEXT: retl
3131
;
3232
; X64-SSE-LABEL: scalar_fsub_neg0_undef:
3333
; X64-SSE: # %bb.0:
@@ -37,10 +37,10 @@ define float @scalar_fsub_neg0_undef(float %x) nounwind {
3737
}
3838

3939
define float @scalar_fneg_undef(float %x) nounwind {
40-
; X32-SSE-LABEL: scalar_fneg_undef:
41-
; X32-SSE: # %bb.0:
42-
; X32-SSE-NEXT: fldz
43-
; X32-SSE-NEXT: retl
40+
; X86-SSE-LABEL: scalar_fneg_undef:
41+
; X86-SSE: # %bb.0:
42+
; X86-SSE-NEXT: fldz
43+
; X86-SSE-NEXT: retl
4444
;
4545
; X64-SSE-LABEL: scalar_fneg_undef:
4646
; X64-SSE: # %bb.0:
@@ -50,9 +50,9 @@ define float @scalar_fneg_undef(float %x) nounwind {
5050
}
5151

5252
define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind {
53-
; X32-SSE-LABEL: fsub_neg0_undef:
54-
; X32-SSE: # %bb.0:
55-
; X32-SSE-NEXT: retl
53+
; X86-SSE-LABEL: fsub_neg0_undef:
54+
; X86-SSE: # %bb.0:
55+
; X86-SSE-NEXT: retl
5656
;
5757
; X64-SSE-LABEL: fsub_neg0_undef:
5858
; X64-SSE: # %bb.0:
@@ -62,9 +62,9 @@ define <4 x float> @fsub_neg0_undef(<4 x float> %Q) nounwind {
6262
}
6363

6464
define <4 x float> @fneg_undef(<4 x float> %Q) nounwind {
65-
; X32-SSE-LABEL: fneg_undef:
66-
; X32-SSE: # %bb.0:
67-
; X32-SSE-NEXT: retl
65+
; X86-SSE-LABEL: fneg_undef:
66+
; X86-SSE: # %bb.0:
67+
; X86-SSE-NEXT: retl
6868
;
6969
; X64-SSE-LABEL: fneg_undef:
7070
; X64-SSE: # %bb.0:
@@ -74,9 +74,9 @@ define <4 x float> @fneg_undef(<4 x float> %Q) nounwind {
7474
}
7575

7676
define <4 x float> @fsub_neg0_undef_elts_undef(<4 x float> %x) {
77-
; X32-SSE-LABEL: fsub_neg0_undef_elts_undef:
78-
; X32-SSE: # %bb.0:
79-
; X32-SSE-NEXT: retl
77+
; X86-SSE-LABEL: fsub_neg0_undef_elts_undef:
78+
; X86-SSE: # %bb.0:
79+
; X86-SSE-NEXT: retl
8080
;
8181
; X64-SSE-LABEL: fsub_neg0_undef_elts_undef:
8282
; X64-SSE: # %bb.0:
@@ -87,12 +87,12 @@ define <4 x float> @fsub_neg0_undef_elts_undef(<4 x float> %x) {
8787

8888
; This test verifies that we generate an FP subtraction because "0.0 - x" is not an fneg.
8989
define <4 x float> @t2(<4 x float> %Q) nounwind {
90-
; X32-SSE-LABEL: t2:
91-
; X32-SSE: # %bb.0:
92-
; X32-SSE-NEXT: xorps %xmm1, %xmm1
93-
; X32-SSE-NEXT: subps %xmm0, %xmm1
94-
; X32-SSE-NEXT: movaps %xmm1, %xmm0
95-
; X32-SSE-NEXT: retl
90+
; X86-SSE-LABEL: t2:
91+
; X86-SSE: # %bb.0:
92+
; X86-SSE-NEXT: xorps %xmm1, %xmm1
93+
; X86-SSE-NEXT: subps %xmm0, %xmm1
94+
; X86-SSE-NEXT: movaps %xmm1, %xmm0
95+
; X86-SSE-NEXT: retl
9696
;
9797
; X64-SSE-LABEL: t2:
9898
; X64-SSE: # %bb.0:
@@ -116,33 +116,33 @@ define <4 x float> @t2(<4 x float> %Q) nounwind {
116116
; movd (move to xmm return register)
117117

118118
define <2 x float> @fneg_bitcast(i64 %i) nounwind {
119-
; X32-SSE1-LABEL: fneg_bitcast:
120-
; X32-SSE1: # %bb.0:
121-
; X32-SSE1-NEXT: pushl %ebp
122-
; X32-SSE1-NEXT: movl %esp, %ebp
123-
; X32-SSE1-NEXT: andl $-16, %esp
124-
; X32-SSE1-NEXT: subl $16, %esp
125-
; X32-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
126-
; X32-SSE1-NEXT: movl 12(%ebp), %ecx
127-
; X32-SSE1-NEXT: xorl %eax, %ecx
128-
; X32-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
129-
; X32-SSE1-NEXT: xorl 8(%ebp), %eax
130-
; X32-SSE1-NEXT: movl %eax, (%esp)
131-
; X32-SSE1-NEXT: movaps (%esp), %xmm0
132-
; X32-SSE1-NEXT: movl %ebp, %esp
133-
; X32-SSE1-NEXT: popl %ebp
134-
; X32-SSE1-NEXT: retl
119+
; X86-SSE1-LABEL: fneg_bitcast:
120+
; X86-SSE1: # %bb.0:
121+
; X86-SSE1-NEXT: pushl %ebp
122+
; X86-SSE1-NEXT: movl %esp, %ebp
123+
; X86-SSE1-NEXT: andl $-16, %esp
124+
; X86-SSE1-NEXT: subl $16, %esp
125+
; X86-SSE1-NEXT: movl $-2147483648, %eax # imm = 0x80000000
126+
; X86-SSE1-NEXT: movl 12(%ebp), %ecx
127+
; X86-SSE1-NEXT: xorl %eax, %ecx
128+
; X86-SSE1-NEXT: movl %ecx, {{[0-9]+}}(%esp)
129+
; X86-SSE1-NEXT: xorl 8(%ebp), %eax
130+
; X86-SSE1-NEXT: movl %eax, (%esp)
131+
; X86-SSE1-NEXT: movaps (%esp), %xmm0
132+
; X86-SSE1-NEXT: movl %ebp, %esp
133+
; X86-SSE1-NEXT: popl %ebp
134+
; X86-SSE1-NEXT: retl
135135
;
136-
; X32-SSE2-LABEL: fneg_bitcast:
137-
; X32-SSE2: # %bb.0:
138-
; X32-SSE2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
139-
; X32-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
140-
; X32-SSE2-NEXT: xorl %eax, %ecx
141-
; X32-SSE2-NEXT: movd %ecx, %xmm1
142-
; X32-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax
143-
; X32-SSE2-NEXT: movd %eax, %xmm0
144-
; X32-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
145-
; X32-SSE2-NEXT: retl
136+
; X86-SSE2-LABEL: fneg_bitcast:
137+
; X86-SSE2: # %bb.0:
138+
; X86-SSE2-NEXT: movl $-2147483648, %eax # imm = 0x80000000
139+
; X86-SSE2-NEXT: movl {{[0-9]+}}(%esp), %ecx
140+
; X86-SSE2-NEXT: xorl %eax, %ecx
141+
; X86-SSE2-NEXT: movd %ecx, %xmm1
142+
; X86-SSE2-NEXT: xorl {{[0-9]+}}(%esp), %eax
143+
; X86-SSE2-NEXT: movd %eax, %xmm0
144+
; X86-SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
145+
; X86-SSE2-NEXT: retl
146146
;
147147
; X64-SSE1-LABEL: fneg_bitcast:
148148
; X64-SSE1: # %bb.0:
@@ -164,10 +164,10 @@ define <2 x float> @fneg_bitcast(i64 %i) nounwind {
164164
}
165165

166166
define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) {
167-
; X32-SSE-LABEL: fneg_undef_elts_v4f32:
168-
; X32-SSE: # %bb.0:
169-
; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
170-
; X32-SSE-NEXT: retl
167+
; X86-SSE-LABEL: fneg_undef_elts_v4f32:
168+
; X86-SSE: # %bb.0:
169+
; X86-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
170+
; X86-SSE-NEXT: retl
171171
;
172172
; X64-SSE-LABEL: fneg_undef_elts_v4f32:
173173
; X64-SSE: # %bb.0:
@@ -180,9 +180,9 @@ define <4 x float> @fneg_undef_elts_v4f32(<4 x float> %x) {
180180
; This isn't fneg, but similarly check that (X - 0.0) is simplified.
181181

182182
define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) {
183-
; X32-SSE-LABEL: fsub0_undef_elts_v4f32:
184-
; X32-SSE: # %bb.0:
185-
; X32-SSE-NEXT: retl
183+
; X86-SSE-LABEL: fsub0_undef_elts_v4f32:
184+
; X86-SSE: # %bb.0:
185+
; X86-SSE-NEXT: retl
186186
;
187187
; X64-SSE-LABEL: fsub0_undef_elts_v4f32:
188188
; X64-SSE: # %bb.0:
@@ -192,10 +192,10 @@ define <4 x float> @fsub0_undef_elts_v4f32(<4 x float> %x) {
192192
}
193193

194194
define <4 x float> @fneg(<4 x float> %Q) nounwind {
195-
; X32-SSE-LABEL: fneg:
196-
; X32-SSE: # %bb.0:
197-
; X32-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
198-
; X32-SSE-NEXT: retl
195+
; X86-SSE-LABEL: fneg:
196+
; X86-SSE: # %bb.0:
197+
; X86-SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0
198+
; X86-SSE-NEXT: retl
199199
;
200200
; X64-SSE-LABEL: fneg:
201201
; X64-SSE: # %bb.0:

0 commit comments

Comments
 (0)