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alexey-bataevalexey-bataev
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[SLP][TTI][X86]Add addsub pattern cost estimation. (llvm#76461)
SLP/TTI do not know about the cost estimation for addsub pattern, supported by X86. Previously the support for pattern detection was added (seeTTI::isLegalAltInstr), but the cost still did not estimated properly.
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8 files changed

+94
-19
lines changed

8 files changed

+94
-19
lines changed

‎llvm/include/llvm/Analysis/TargetTransformInfo.h

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1243,6 +1243,18 @@ class TargetTransformInfo {
12431243
ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
12441244
const Instruction *CxtI = nullptr) const;
12451245

1246+
/// Returns the cost estimation for alternating opcode pattern that can be
1247+
/// lowered to a single instruction on the target. In X86 this is for the
1248+
/// addsub instruction which corrsponds to a Shuffle + Fadd + FSub pattern in
1249+
/// IR. This function expects two opcodes: \p Opcode1 and \p Opcode2 being
1250+
/// selected by \p OpcodeMask. The mask contains one bit per lane and is a `0`
1251+
/// when \p Opcode0 is selected and `1` when Opcode1 is selected.
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/// \p VecTy is the vector type of the instruction to be generated.
1253+
InstructionCost getAltInstrCost(
1254+
VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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const SmallBitVector &OpcodeMask,
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TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const;
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/// \return The cost of a shuffle instruction of kind Kind and of type Tp.
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/// The exact mask may be passed as Mask, or else the array will be empty.
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/// The index and subtype parameters are used by the subvector insertion and
@@ -1944,6 +1956,10 @@ class TargetTransformInfo::Concept {
19441956
unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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OperandValueInfo Opd1Info, OperandValueInfo Opd2Info,
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ArrayRef<const Value *> Args, const Instruction *CxtI = nullptr) = 0;
1959+
virtual InstructionCost getAltInstrCost(
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VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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const SmallBitVector &OpcodeMask,
1962+
TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput) const = 0;
19471963

19481964
virtual InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask,
@@ -2555,6 +2571,12 @@ class TargetTransformInfo::Model final : public TargetTransformInfo::Concept {
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return Impl.getArithmeticInstrCost(Opcode, Ty, CostKind, Opd1Info, Opd2Info,
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Args, CxtI);
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}
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InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
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unsigned Opcode1,
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const SmallBitVector &OpcodeMask,
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TTI::TargetCostKind CostKind) const override {
2578+
return Impl.getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
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}
25582580

25592581
InstructionCost getShuffleCost(ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask,

‎llvm/include/llvm/Analysis/TargetTransformInfoImpl.h

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -554,6 +554,13 @@ class TargetTransformInfoImplBase {
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return 1;
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}
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557+
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
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unsigned Opcode1,
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const SmallBitVector &OpcodeMask,
560+
TTI::TargetCostKind CostKind) const {
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return InstructionCost::getInvalid();
562+
}
563+
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InstructionCost
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getShuffleCost(TTI::ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,

‎llvm/lib/Analysis/TargetTransformInfo.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -862,6 +862,15 @@ InstructionCost TargetTransformInfo::getArithmeticInstrCost(
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return Cost;
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}
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865+
InstructionCost TargetTransformInfo::getAltInstrCost(
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VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
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const SmallBitVector &OpcodeMask, TTI::TargetCostKind CostKind) const {
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InstructionCost Cost =
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TTIImpl->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
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assert(Cost >= 0 && "TTI should not produce negative costs!");
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return Cost;
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}
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InstructionCost TargetTransformInfo::getShuffleCost(
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ShuffleKind Kind, VectorType *Ty, ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind, int Index, VectorType *SubTp,

‎llvm/lib/Target/X86/X86TargetTransformInfo.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1459,6 +1459,15 @@ InstructionCost X86TTIImpl::getArithmeticInstrCost(
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Args, CxtI);
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}
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InstructionCost
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X86TTIImpl::getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
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unsigned Opcode1, const SmallBitVector &OpcodeMask,
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TTI::TargetCostKind CostKind) const {
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if (isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask))
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return TTI::TCC_Basic;
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return InstructionCost::getInvalid();
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}
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InstructionCost X86TTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
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VectorType *BaseTp,
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ArrayRef<int> Mask,

‎llvm/lib/Target/X86/X86TargetTransformInfo.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,11 @@ class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
142142
const Instruction *CxtI = nullptr);
143+
InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0,
144+
unsigned Opcode1,
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const SmallBitVector &OpcodeMask,
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TTI::TargetCostKind CostKind) const;
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind, int Index,

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8428,6 +8428,25 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef<Value *> VectorizedVals,
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Mask);
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VecCost += TTI->getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc,
84308430
FinalVecTy, Mask);
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// Patterns like [fadd,fsub] can be combined into a single instruction
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// in x86. Reordering them into [fsub,fadd] blocks this pattern. So we
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// need to take into account their order when looking for the most used
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// order.
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unsigned Opcode0 = E->getOpcode();
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unsigned Opcode1 = E->getAltOpcode();
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// The opcode mask selects between the two opcodes.
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SmallBitVector OpcodeMask(E->Scalars.size(), false);
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for (unsigned Lane : seq<unsigned>(0, E->Scalars.size()))
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if (cast<Instruction>(E->Scalars[Lane])->getOpcode() == Opcode1)
8441+
OpcodeMask.set(Lane);
8442+
// If this pattern is supported by the target then we consider the
8443+
// order.
8444+
if (TTI->isLegalAltInstr(VecTy, Opcode0, Opcode1, OpcodeMask)) {
8445+
InstructionCost AltVecCost =
8446+
TTI->getAltInstrCost(VecTy, Opcode0, Opcode1, OpcodeMask, CostKind);
8447+
return AltVecCost < VecCost ? AltVecCost : VecCost;
8448+
}
8449+
// TODO: Check the reverse order too.
84318450
return VecCost;
84328451
};
84338452
return GetCostDiff(GetScalarCost, GetVectorCost);

‎llvm/test/Transforms/SLPVectorizer/X86/supernode.ll

Lines changed: 12 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -103,21 +103,23 @@ define void @test_supernode_addsub_alt(ptr %Aarray, ptr %Barray, ptr %Carray, pt
103103
; ENABLED-LABEL: @test_supernode_addsub_alt(
104104
; ENABLED-NEXT: entry:
105105
; ENABLED-NEXT: [[IDXA1:%.*]] = getelementptr inbounds double, ptr [[AARRAY:%.*]], i64 1
106-
; ENABLED-NEXT: [[IDXB1:%.*]] = getelementptr inbounds double, ptr [[BARRAY:%.*]], i64 1
107106
; ENABLED-NEXT: [[IDXC1:%.*]] = getelementptr inbounds double, ptr [[CARRAY:%.*]], i64 1
108-
; ENABLED-NEXT: [[IDXS1:%.*]] = getelementptr inbounds double, ptr [[SARRAY:%.*]], i64 1
109107
; ENABLED-NEXT: [[A0:%.*]] = load double, ptr [[AARRAY]], align 8
110108
; ENABLED-NEXT: [[A1:%.*]] = load double, ptr [[IDXA1]], align 8
111-
; ENABLED-NEXT: [[B0:%.*]] = load double, ptr [[BARRAY]], align 8
112-
; ENABLED-NEXT: [[B1:%.*]] = load double, ptr [[IDXB1]], align 8
113109
; ENABLED-NEXT: [[C0:%.*]] = load double, ptr [[CARRAY]], align 8
114110
; ENABLED-NEXT: [[C1:%.*]] = load double, ptr [[IDXC1]], align 8
115-
; ENABLED-NEXT: [[SUBA0B0:%.*]] = fsub fast double [[A0]], [[B0]]
116-
; ENABLED-NEXT: [[ADDB1C1:%.*]] = fadd fast double [[B1]], [[C1]]
117-
; ENABLED-NEXT: [[SUB0:%.*]] = fsub fast double [[SUBA0B0]], [[C0]]
118-
; ENABLED-NEXT: [[ADD1:%.*]] = fadd fast double [[ADDB1C1]], [[A1]]
119-
; ENABLED-NEXT: store double [[SUB0]], ptr [[SARRAY]], align 8
120-
; ENABLED-NEXT: store double [[ADD1]], ptr [[IDXS1]], align 8
111+
; ENABLED-NEXT: [[TMP0:%.*]] = load <2 x double>, ptr [[BARRAY:%.*]], align 8
112+
; ENABLED-NEXT: [[TMP1:%.*]] = insertelement <2 x double> poison, double [[A0]], i32 0
113+
; ENABLED-NEXT: [[TMP2:%.*]] = insertelement <2 x double> [[TMP1]], double [[C1]], i32 1
114+
; ENABLED-NEXT: [[TMP3:%.*]] = fsub fast <2 x double> [[TMP2]], [[TMP0]]
115+
; ENABLED-NEXT: [[TMP4:%.*]] = fadd fast <2 x double> [[TMP2]], [[TMP0]]
116+
; ENABLED-NEXT: [[TMP5:%.*]] = shufflevector <2 x double> [[TMP3]], <2 x double> [[TMP4]], <2 x i32> <i32 0, i32 3>
117+
; ENABLED-NEXT: [[TMP6:%.*]] = insertelement <2 x double> poison, double [[C0]], i32 0
118+
; ENABLED-NEXT: [[TMP7:%.*]] = insertelement <2 x double> [[TMP6]], double [[A1]], i32 1
119+
; ENABLED-NEXT: [[TMP8:%.*]] = fsub fast <2 x double> [[TMP5]], [[TMP7]]
120+
; ENABLED-NEXT: [[TMP9:%.*]] = fadd fast <2 x double> [[TMP5]], [[TMP7]]
121+
; ENABLED-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP8]], <2 x double> [[TMP9]], <2 x i32> <i32 0, i32 3>
122+
; ENABLED-NEXT: store <2 x double> [[TMP10]], ptr [[SARRAY:%.*]], align 8
121123
; ENABLED-NEXT: ret void
122124
;
123125
entry:

‎llvm/test/Transforms/SLPVectorizer/X86/vectorize-widest-phis.ll

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -12,22 +12,24 @@ define void @foo() {
1212
; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> [[TMP0]], float [[CONV]], i32 1
1313
; CHECK-NEXT: br label [[BB2:%.*]]
1414
; CHECK: bb2:
15-
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP10:%.*]], [[BB3:%.*]] ]
15+
; CHECK-NEXT: [[TMP2:%.*]] = phi <4 x float> [ [[TMP1]], [[BB1]] ], [ [[TMP14:%.*]], [[BB3:%.*]] ]
1616
; CHECK-NEXT: [[TMP3:%.*]] = load double, ptr undef, align 8
1717
; CHECK-NEXT: br i1 undef, label [[BB3]], label [[BB4:%.*]]
1818
; CHECK: bb4:
1919
; CHECK-NEXT: [[TMP4:%.*]] = fpext <4 x float> [[TMP2]] to <4 x double>
2020
; CHECK-NEXT: [[CONV2:%.*]] = uitofp i16 undef to double
21-
; CHECK-NEXT: [[ADD1:%.*]] = fadd double [[TMP3]], [[CONV2]]
22-
; CHECK-NEXT: [[SUB1:%.*]] = fsub double undef, undef
23-
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x double> <double poison, double poison, double undef, double undef>, double [[SUB1]], i32 0
24-
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x double> [[TMP5]], double [[ADD1]], i32 1
25-
; CHECK-NEXT: [[TMP7:%.*]] = fcmp ogt <4 x double> [[TMP6]], [[TMP4]]
26-
; CHECK-NEXT: [[TMP8:%.*]] = fptrunc <4 x double> [[TMP6]] to <4 x float>
27-
; CHECK-NEXT: [[TMP9:%.*]] = select <4 x i1> [[TMP7]], <4 x float> [[TMP2]], <4 x float> [[TMP8]]
21+
; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[TMP3]], i32 1
22+
; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x double> <double undef, double poison>, double [[CONV2]], i32 1
23+
; CHECK-NEXT: [[TMP7:%.*]] = fsub <2 x double> [[TMP5]], [[TMP6]]
24+
; CHECK-NEXT: [[TMP8:%.*]] = fadd <2 x double> [[TMP5]], [[TMP6]]
25+
; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x double> [[TMP7]], <2 x double> [[TMP8]], <2 x i32> <i32 0, i32 3>
26+
; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x double> [[TMP9]], <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
27+
; CHECK-NEXT: [[TMP11:%.*]] = fcmp ogt <4 x double> [[TMP10]], [[TMP4]]
28+
; CHECK-NEXT: [[TMP12:%.*]] = fptrunc <4 x double> [[TMP10]] to <4 x float>
29+
; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x float> [[TMP2]], <4 x float> [[TMP12]]
2830
; CHECK-NEXT: br label [[BB3]]
2931
; CHECK: bb3:
30-
; CHECK-NEXT: [[TMP10]] = phi <4 x float> [ [[TMP9]], [[BB4]] ], [ [[TMP2]], [[BB2]] ]
32+
; CHECK-NEXT: [[TMP14]] = phi <4 x float> [ [[TMP13]], [[BB4]] ], [ [[TMP2]], [[BB2]] ]
3133
; CHECK-NEXT: br label [[BB2]]
3234
;
3335
entry:

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