Merged main:c503758ab6a4eacd3ef671a4a5ccf813995d4456 into amd-gfx:17cdfa7e29b1

Local branch amd-gfx 17cdfa7 Merged main:5b41eb3a6dcd92711b4adf946e4d9d29c3886007 into amd-gfx:add913c7d296
Remote branch main c503758 [CodeGen] Use std::pair<MCRegister, Register> to match return from MRI.liveins(). NFC

Author: SC llvm team

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 509567
+#define LLVM_MAIN_REVISION 509568
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/CodeGen/MIRPrinter.cpp

@@ -329,7 +329,7 @@ void MIRPrinter::convert(yaml::MachineFunction &MF,
   }
 
   // Print the live ins.
-  for (std::pair<unsigned, unsigned> LI : RegInfo.liveins()) {
+  for (std::pair<MCRegister, Register> LI : RegInfo.liveins()) {
     yaml::MachineFunctionLiveIn LiveIn;
     printRegMIR(LI.first, LiveIn.Register, TRI);
     if (LI.second)

llvm/lib/CodeGen/RDFGraph.cpp

@@ -913,7 +913,7 @@ void DataFlowGraph::build(const Config &config) {
   // Collect function live-ins and entry block live-ins.
   MachineBasicBlock &EntryB = *EA.Addr->getCode();
   assert(EntryB.pred_empty() && "Function entry block has predecessors");
-  for (std::pair<unsigned, unsigned> P : MRI.liveins())
+  for (std::pair<MCRegister, Register> P : MRI.liveins())
     LiveIns.insert(RegisterRef(P.first));
   if (MRI.tracksLiveness()) {
     for (auto I : EntryB.liveins())

llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

@@ -675,7 +675,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
 
   DenseMap<unsigned, unsigned> LiveInMap;
   if (!FuncInfo->ArgDbgValues.empty())
-    for (std::pair<unsigned, unsigned> LI : RegInfo->liveins())
+    for (std::pair<MCRegister, Register> LI : RegInfo->liveins())
       if (LI.second)
         LiveInMap.insert(LI);
 

llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

@@ -1162,7 +1162,7 @@ int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const {
   }
 
   const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
-  for (std::pair<unsigned, unsigned> LI : MRI.liveins()) {
+  for (std::pair<MCRegister, Register> LI : MRI.liveins()) {
     Register Reg = LI.first;
     if (Reg.isVirtual() || !IndirectRC->contains(Reg))
       continue;

llvm/lib/Target/Hexagon/HexagonBitTracker.cpp

@@ -1287,7 +1287,7 @@ unsigned HexagonEvaluator::getNextPhysReg(unsigned PReg, unsigned Width) const {
 }
 
 unsigned HexagonEvaluator::getVirtRegFor(unsigned PReg) const {
-  for (std::pair<unsigned,unsigned> P : MRI.liveins())
+  for (std::pair<MCRegister, Register> P : MRI.liveins())
     if (P.first == PReg)
       return P.second;
   return 0;

llvm/lib/Target/X86/X86ISelLoweringCall.cpp

@@ -1903,7 +1903,7 @@ SDValue X86TargetLowering::LowerFormalArguments(
   if (shouldDisableArgRegFromCSR(CallConv) ||
       F.hasFnAttribute("no_caller_saved_registers")) {
     MachineRegisterInfo &MRI = MF.getRegInfo();
-    for (std::pair<Register, Register> Pair : MRI.liveins())
+    for (std::pair<MCRegister, Register> Pair : MRI.liveins())
       MRI.disableCalleeSavedRegister(Pair.first);
   }
 

llvm/lib/Target/X86/X86VZeroUpper.cpp

@@ -136,7 +136,7 @@ static bool isYmmOrZmmReg(unsigned Reg) {
 }
 
 static bool checkFnHasLiveInYmmOrZmm(MachineRegisterInfo &MRI) {
-  for (std::pair<unsigned, unsigned> LI : MRI.liveins())
+  for (std::pair<MCRegister, Register> LI : MRI.liveins())
     if (isYmmOrZmmReg(LI.first))
       return true;