[RISCV] Update Zicntr and Zihpm to version 2p0 (llvm#66323)

Author: jacquesguan

clang/test/Preprocessor/riscv-target-features.c

@@ -643,7 +643,7 @@
 // RUN: %clang -target riscv64-unknown-linux-gnu \
 // RUN: -march=rv64izicntr -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZICNTR-EXT %s
-// CHECK-ZICNTR-EXT: __riscv_zicntr 1000000{{$}}
+// CHECK-ZICNTR-EXT: __riscv_zicntr 2000000{{$}}
 
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izicsr2p0 -x c -E -dM %s \
@@ -677,6 +677,14 @@
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZIHINTPAUSE-EXT %s
 // CHECK-ZIHINTPAUSE-EXT: __riscv_zihintpause 2000000{{$}}
 
+// RUN: %clang -target riscv32-unknown-linux-gnu \
+// RUN: -march=rv32izihpm -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHPM-EXT %s
+// RUN: %clang -target riscv64-unknown-linux-gnu \
+// RUN: -march=rv64izihpm -x c -E -dM %s \
+// RUN: -o - | FileCheck --check-prefix=CHECK-ZIHPM-EXT %s
+// CHECK-ZIHPM-EXT: __riscv_zihpm 2000000{{$}}
+
 // RUN: %clang -target riscv32-unknown-linux-gnu \
 // RUN: -march=rv32izk1p0 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZK-EXT %s

llvm/lib/Support/RISCVISAInfo.cpp

@@ -116,12 +116,12 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
     {"zicbom", RISCVExtensionVersion{1, 0}},
     {"zicbop", RISCVExtensionVersion{1, 0}},
     {"zicboz", RISCVExtensionVersion{1, 0}},
-    {"zicntr", RISCVExtensionVersion{1, 0}},
+    {"zicntr", RISCVExtensionVersion{2, 0}},
     {"zicsr", RISCVExtensionVersion{2, 0}},
     {"zifencei", RISCVExtensionVersion{2, 0}},
     {"zihintntl", RISCVExtensionVersion{1, 0}},
     {"zihintpause", RISCVExtensionVersion{2, 0}},
-    {"zihpm", RISCVExtensionVersion{1, 0}},
+    {"zihpm", RISCVExtensionVersion{2, 0}},
 
     {"zk", RISCVExtensionVersion{1, 0}},
     {"zkn", RISCVExtensionVersion{1, 0}},

llvm/test/CodeGen/RISCV/attributes.ll

@@ -241,8 +241,8 @@
 ; RV32ZCMT: .attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV32ZICSR: .attribute 5, "rv32i2p1_zicsr2p0"
 ; RV32ZIFENCEI: .attribute 5, "rv32i2p1_zifencei2p0"
-; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr1p0_zicsr2p0"
-; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm1p0"
+; RV32ZICNTR: .attribute 5, "rv32i2p1_zicntr2p0_zicsr2p0"
+; RV32ZIHPM: .attribute 5, "rv32i2p1_zicsr2p0_zihpm2p0"
 ; RV32ZFA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV32ZVBB: .attribute 5, "rv32i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
 ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"
@@ -330,8 +330,8 @@
 ; RV64ZCMT: .attribute 5, "rv64i2p1_zicsr2p0_zca1p0_zcmt1p0"
 ; RV64ZICSR: .attribute 5, "rv64i2p1_zicsr2p0"
 ; RV64ZIFENCEI: .attribute 5, "rv64i2p1_zifencei2p0"
-; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr1p0_zicsr2p0"
-; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm1p0"
+; RV64ZICNTR: .attribute 5, "rv64i2p1_zicntr2p0_zicsr2p0"
+; RV64ZIHPM: .attribute 5, "rv64i2p1_zicsr2p0_zihpm2p0"
 ; RV64ZFA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfa0p2"
 ; RV64ZVBB: .attribute 5, "rv64i2p1_zicsr2p0_zvbb1p0_zve32x1p0_zvkb1p0_zvl32b1p0"
 ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0"

llvm/unittests/Support/RISCVISAInfoTest.cpp

@@ -644,12 +644,12 @@ R"(All available -march extensions for RISC-V
 	zicbom              1.0
 	zicbop              1.0
 	zicboz              1.0
-	zicntr              1.0
+	zicntr              2.0
 	zicsr               2.0
 	zifencei            2.0
 	zihintntl           1.0
 	zihintpause         2.0
-	zihpm               1.0
+	zihpm               2.0
 	zmmul               1.0
 	zawrs               1.0
 	zfh                 1.0