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LukacmahassnaaHamdi
Lukacma
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hassnaaHamdi
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[AArch64] Implement NEON vscale intrinsics (llvm#100347)
This patch implements following intrinsics: ``` float16x4_t vscale_f16(float16x4_t vn, int16x4_t vm) float16x8_t vscaleq_f16(float16x8_t vn, int16x8_t vm) float32x2_t vscale_f32(float32x2_t vn, int32x2_t vm) float32x4_t vscaleq_f32(float32x4_t vn, int32x4_t vm) float64x2_t vscaleq_f64(float64x2_t vn, int64x2_t vm) ``` as defined in ARM-software/acle#323 Co-authored-by: Hassnaa Hamdi <[email protected]>
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‎clang/include/clang/Basic/arm_neon.td

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@@ -2126,3 +2126,9 @@ let ArchGuard = "defined(__aarch64__)", TargetGuard = "neon,faminmax" in {
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def FAMIN : WInst<"vamin", "...", "fhQdQfQh">;
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def FAMAX : WInst<"vamax", "...", "fhQdQfQh">;
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}
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let ArchGuard = "defined(__aarch64__)", TargetGuard = "fp8,neon" in {
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// fscale
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def FSCALE_V128 : WInst<"vscale", "..(.S)", "QdQfQh">;
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def FSCALE_V64 : WInst<"vscale", "(.q)(.q)(.qS)", "fh">;
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}

‎clang/lib/CodeGen/CGBuiltin.cpp

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@@ -13573,6 +13573,14 @@ Value *CodeGenFunction::EmitAArch64BuiltinExpr(unsigned BuiltinID,
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Int = Intrinsic::aarch64_neon_famax;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "famax");
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}
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case NEON::BI__builtin_neon_vscale_f16:
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case NEON::BI__builtin_neon_vscaleq_f16:
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case NEON::BI__builtin_neon_vscale_f32:
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case NEON::BI__builtin_neon_vscaleq_f32:
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case NEON::BI__builtin_neon_vscaleq_f64: {
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Int = Intrinsic::aarch64_neon_fp8_fscale;
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return EmitNeonCall(CGM.getIntrinsic(Int, Ty), Ops, "fscale");
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}
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}
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}
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‎clang/test/CodeGen/aarch64-neon-fp8-intrinsics/acle_neon_fscale.c

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@@ -0,0 +1,58 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4
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#include <arm_neon.h>
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -O3 -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +fp8 -S -O3 -o /dev/null %s
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// CHECK-LABEL: define dso_local <4 x half> @test_vscale_f16(
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// CHECK-SAME: <4 x half> noundef [[VN:%.*]], <4 x i16> noundef [[VM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[FSCALE2_I:%.*]] = tail call <4 x half> @llvm.aarch64.neon.fp8.fscale.v4f16(<4 x half> [[VN]], <4 x i16> [[VM]])
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// CHECK-NEXT: ret <4 x half> [[FSCALE2_I]]
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//
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float16x4_t test_vscale_f16(float16x4_t vn, int16x4_t vm) {
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return vscale_f16(vn, vm);
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}
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// CHECK-LABEL: define dso_local <8 x half> @test_vscaleq_f16(
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// CHECK-SAME: <8 x half> noundef [[VN:%.*]], <8 x i16> noundef [[VM:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[FSCALE2_I:%.*]] = tail call <8 x half> @llvm.aarch64.neon.fp8.fscale.v8f16(<8 x half> [[VN]], <8 x i16> [[VM]])
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// CHECK-NEXT: ret <8 x half> [[FSCALE2_I]]
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//
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float16x8_t test_vscaleq_f16(float16x8_t vn, int16x8_t vm) {
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return vscaleq_f16(vn, vm);
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}
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// CHECK-LABEL: define dso_local <2 x float> @test_vscale_f32(
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// CHECK-SAME: <2 x float> noundef [[VN:%.*]], <2 x i32> noundef [[VM:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[FSCALE2_I:%.*]] = tail call <2 x float> @llvm.aarch64.neon.fp8.fscale.v2f32(<2 x float> [[VN]], <2 x i32> [[VM]])
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// CHECK-NEXT: ret <2 x float> [[FSCALE2_I]]
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//
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float32x2_t test_vscale_f32(float32x2_t vn, int32x2_t vm) {
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return vscale_f32(vn, vm);
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}
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// CHECK-LABEL: define dso_local <4 x float> @test_vscaleq_f32(
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// CHECK-SAME: <4 x float> noundef [[VN:%.*]], <4 x i32> noundef [[VM:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[FSCALE2_I:%.*]] = tail call <4 x float> @llvm.aarch64.neon.fp8.fscale.v4f32(<4 x float> [[VN]], <4 x i32> [[VM]])
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// CHECK-NEXT: ret <4 x float> [[FSCALE2_I]]
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//
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float32x4_t test_vscaleq_f32(float32x4_t vn, int32x4_t vm) {
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return vscaleq_f32(vn, vm);
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}
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// CHECK-LABEL: define dso_local <2 x double> @test_vscale_f64(
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// CHECK-SAME: <2 x double> noundef [[VN:%.*]], <2 x i64> noundef [[VM:%.*]]) local_unnamed_addr #[[ATTR0]] {
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[FSCALE2_I:%.*]] = tail call <2 x double> @llvm.aarch64.neon.fp8.fscale.v2f64(<2 x double> [[VN]], <2 x i64> [[VM]])
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// CHECK-NEXT: ret <2 x double> [[FSCALE2_I]]
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//
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float64x2_t test_vscale_f64(float64x2_t vn, int64x2_t vm) {
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return vscaleq_f64(vn, vm);
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}

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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@@ -563,6 +563,13 @@ let TargetPrefix = "aarch64", IntrProperties = [IntrNoMem] in {
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def int_aarch64_neon_vcmla_rot90 : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot180 : AdvSIMD_3VectorArg_Intrinsic;
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def int_aarch64_neon_vcmla_rot270 : AdvSIMD_3VectorArg_Intrinsic;
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// FP8 fscale
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def int_aarch64_neon_fp8_fscale : DefaultAttrsIntrinsic<
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[llvm_anyvector_ty],
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[LLVMMatchType<0>,
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LLVMVectorOfBitcastsToInt<0>],
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[IntrNoMem]>;
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}
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let TargetPrefix = "aarch64" in {

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

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@@ -6243,6 +6243,26 @@ multiclass SIMDThreeSameVectorDOT4<string asm> {
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V128, v4f32, v16i8, null_frag>;
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}
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let mayRaiseFPException = 1, Uses = [FPCR] in
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multiclass SIMDThreeVectorFscale<bit U, bit S, bits<3> opc,
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string asm, SDPatternOperator OpNode> {
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def v4f16 : BaseSIMDThreeSameVector<0, U, {S,0b10}, {0b00,opc}, V64,
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asm, ".4h",
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[(set (v4f16 V64:$Rd), (OpNode (v4f16 V64:$Rn), (v4i16 V64:$Rm)))]>;
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def v8f16 : BaseSIMDThreeSameVector<1, U, {S,0b10}, {0b00,opc}, V128,
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asm, ".8h",
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[(set (v8f16 V128:$Rd), (OpNode (v8f16 V128:$Rn), (v8i16 V128:$Rm)))]>;
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def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0b01}, {0b11,opc}, V64,
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asm, ".2s",
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[(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2i32 V64:$Rm)))]>;
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def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0b01}, {0b11,opc}, V128,
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asm, ".4s",
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[(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4i32 V128:$Rm)))]>;
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def v2f64 : BaseSIMDThreeSameVector<1, U, {S,0b11}, {0b11,opc}, V128,
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asm, ".2d",
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[(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2i64 V128:$Rm)))]>;
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}
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//----------------------------------------------------------------------------
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// AdvSIMD two register vector instructions.
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//----------------------------------------------------------------------------

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

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Original file line numberDiff line numberDiff line change
@@ -10136,7 +10136,7 @@ let Uses = [FPMR, FPCR], Predicates = [HasFP8] in {
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defm BF2CVTL : SIMDMixedTwoVectorFP8<0b11, "bf2cvtl">;
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defm FCVTN_F16_F8 : SIMDThreeSameSizeVectorCvt<"fcvtn">;
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defm FCVTN_F32_F8 : SIMDThreeVectorCvt<"fcvtn">;
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defm FSCALE : SIMDThreeSameVectorFP<0b1, 0b1, 0b111, "fscale", null_frag>;
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defm FSCALE : SIMDThreeVectorFscale<0b1, 0b1, 0b111, "fscale", int_aarch64_neon_fp8_fscale>;
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} // End let Predicates = [HasFP8]
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// fminimum(abs(a), abs(b)) -> famin(a, b)

‎llvm/test/CodeGen/AArch64/neon-fp8-fscale.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64-linux -mattr=+neon,+fp8 < %s | FileCheck %s
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define <4 x half> @test_fscale_f16(<4 x half> %vn, <4 x i16> %vm) {
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; CHECK-LABEL: test_fscale_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fscale v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%res = tail call <4 x half> @llvm.aarch64.neon.fp8.fscale.v4f16(<4 x half> %vn, <4 x i16> %vm)
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ret <4 x half> %res
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}
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define <8 x half> @test_fscaleq_f16(<8 x half> %vn, <8 x i16> %vm) {
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; CHECK-LABEL: test_fscaleq_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fscale v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%res = tail call <8 x half> @llvm.aarch64.neon.fp8.fscale.v8f16(<8 x half> %vn, <8 x i16> %vm)
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ret <8 x half> %res
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}
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define <2 x float> @test_fscale_f32(<2 x float> %vn, <2 x i32> %vm) {
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; CHECK-LABEL: test_fscale_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fscale v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%res = tail call <2 x float> @llvm.aarch64.neon.fp8.fscale.v2f32(<2 x float> %vn, <2 x i32> %vm)
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ret <2 x float> %res
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}
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define <4 x float> @test_fscaleq_f32(<4 x float> %vn, <4 x i32> %vm) {
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; CHECK-LABEL: test_fscaleq_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fscale v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%res = tail call <4 x float> @llvm.aarch64.neon.fp8.fscale.v4f32(<4 x float> %vn, <4 x i32> %vm)
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ret <4 x float> %res
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}
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define <2 x double> @test_fscaleq_f64(<2 x double> %vn, <2 x i64> %vm) {
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; CHECK-LABEL: test_fscaleq_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fscale v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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%res = tail call <2 x double> @llvm.aarch64.neon.fp8.fscale.v2f64(<2 x double> %vn, <2 x i64> %vm)
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ret <2 x double> %res
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}
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declare <4 x half> @llvm.aarch64.neon.fp8.fscale.v4f16(<4 x half>, <4 x i16>)
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declare <8 x half> @llvm.aarch64.neon.fp8.fscale.v8f16(<8 x half>, <8 x i16>)
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declare <2 x float> @llvm.aarch64.neon.fp8.fscale.v2f32(<2 x float>, <2 x i32>)
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declare <4 x float> @llvm.aarch64.neon.fp8.fscale.v4f32(<4 x float>, <4 x i32>)
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declare <2 x double> @llvm.aarch64.neon.fp8.fscale.v2f64(<2 x double>, <2 x i64>)

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