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davemgreendavemgreen
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[AArch64] Add VSHL knownBits handling.
These can be handled in the same way as other shifts.
1 parent 0b779b0 commit c782e34

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9 files changed

+74
-80
lines changed

9 files changed

+74
-80
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2107,6 +2107,13 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
21072107
Known = KnownBits::ashr(Known, Known2);
21082108
break;
21092109
}
2110+
case AArch64ISD::VSHL: {
2111+
KnownBits Known2;
2112+
Known = DAG.computeKnownBits(Op->getOperand(0), Depth + 1);
2113+
Known2 = DAG.computeKnownBits(Op->getOperand(1), Depth + 1);
2114+
Known = KnownBits::shl(Known, Known2);
2115+
break;
2116+
}
21102117
case AArch64ISD::MOVI: {
21112118
ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
21122119
Known =

‎llvm/test/CodeGen/AArch64/funnel-shift-rot.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -94,9 +94,9 @@ define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
9494
define <4 x i32> @rotl_v4i32_rotl_const_shift(<4 x i32> %x) {
9595
; CHECK-LABEL: rotl_v4i32_rotl_const_shift:
9696
; CHECK: // %bb.0:
97-
; CHECK-NEXT: ushr v1.4s, v0.4s, #29
98-
; CHECK-NEXT: shl v0.4s, v0.4s, #3
99-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
97+
; CHECK-NEXT: shl v1.4s, v0.4s, #3
98+
; CHECK-NEXT: usra v1.4s, v0.4s, #29
99+
; CHECK-NEXT: mov v0.16b, v1.16b
100100
; CHECK-NEXT: ret
101101
%f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
102102
ret <4 x i32> %f
@@ -185,8 +185,8 @@ define <4 x i32> @rotr_v4i32_const_shift(<4 x i32> %x) {
185185
; CHECK-LABEL: rotr_v4i32_const_shift:
186186
; CHECK: // %bb.0:
187187
; CHECK-NEXT: shl v1.4s, v0.4s, #29
188-
; CHECK-NEXT: ushr v0.4s, v0.4s, #3
189-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
188+
; CHECK-NEXT: usra v1.4s, v0.4s, #3
189+
; CHECK-NEXT: mov v0.16b, v1.16b
190190
; CHECK-NEXT: ret
191191
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> <i32 3, i32 3, i32 3, i32 3>)
192192
ret <4 x i32> %f

‎llvm/test/CodeGen/AArch64/rax1.ll

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -10,10 +10,9 @@ define <2 x i64> @rax1(<2 x i64> %x, <2 x i64> %y) {
1010
;
1111
; NOSHA3-LABEL: rax1:
1212
; NOSHA3: // %bb.0:
13-
; NOSHA3-NEXT: ushr v2.2d, v1.2d, #63
14-
; NOSHA3-NEXT: add v1.2d, v1.2d, v1.2d
15-
; NOSHA3-NEXT: orr v1.16b, v1.16b, v2.16b
16-
; NOSHA3-NEXT: eor v0.16b, v0.16b, v1.16b
13+
; NOSHA3-NEXT: add v2.2d, v1.2d, v1.2d
14+
; NOSHA3-NEXT: usra v2.2d, v1.2d, #63
15+
; NOSHA3-NEXT: eor v0.16b, v0.16b, v2.16b
1716
; NOSHA3-NEXT: ret
1817
%a = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> %y, <2 x i64> %y, <2 x i64> <i64 1, i64 1>)
1918
%b = xor <2 x i64> %x, %a

‎llvm/test/CodeGen/AArch64/rotate.ll

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6,10 +6,9 @@
66
define <2 x i64> @testcase(ptr %in) {
77
; CHECK-LABEL: testcase:
88
; CHECK: // %bb.0:
9-
; CHECK-NEXT: ldr q0, [x0]
10-
; CHECK-NEXT: ushr v1.2d, v0.2d, #8
11-
; CHECK-NEXT: shl v0.2d, v0.2d, #56
12-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
9+
; CHECK-NEXT: ldr q1, [x0]
10+
; CHECK-NEXT: shl v0.2d, v1.2d, #56
11+
; CHECK-NEXT: usra v0.2d, v1.2d, #8
1312
; CHECK-NEXT: ret
1413
%1 = load <2 x i64>, ptr %in
1514
%2 = lshr <2 x i64> %1, <i64 8, i64 8>

‎llvm/test/CodeGen/AArch64/srem-seteq-vec-nonsplat.ll

Lines changed: 20 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -83,17 +83,16 @@ define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {
8383
; CHECK-NEXT: mov w9, #9362 // =0x2492
8484
; CHECK-NEXT: movk w8, #46811, lsl #16
8585
; CHECK-NEXT: movk w9, #4681, lsl #16
86-
; CHECK-NEXT: movi v3.4s, #1
8786
; CHECK-NEXT: dup v1.4s, w8
8887
; CHECK-NEXT: dup v2.4s, w9
8988
; CHECK-NEXT: adrp x8, .LCPI3_0
9089
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
90+
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
9191
; CHECK-NEXT: shl v0.4s, v2.4s, #31
92-
; CHECK-NEXT: ushr v1.4s, v2.4s, #1
93-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
94-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
95-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
96-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
92+
; CHECK-NEXT: usra v0.4s, v2.4s, #1
93+
; CHECK-NEXT: movi v2.4s, #1
94+
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
95+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
9796
; CHECK-NEXT: ret
9897
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
9998
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -107,17 +106,16 @@ define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {
107106
; CHECK-NEXT: mov w9, #9362 // =0x2492
108107
; CHECK-NEXT: movk w8, #46811, lsl #16
109108
; CHECK-NEXT: movk w9, #4681, lsl #16
110-
; CHECK-NEXT: movi v3.4s, #1
111109
; CHECK-NEXT: dup v1.4s, w8
112110
; CHECK-NEXT: dup v2.4s, w9
113111
; CHECK-NEXT: adrp x8, .LCPI4_0
114112
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
113+
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
115114
; CHECK-NEXT: shl v0.4s, v2.4s, #31
116-
; CHECK-NEXT: ushr v1.4s, v2.4s, #1
117-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI4_0]
118-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
119-
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
120-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
115+
; CHECK-NEXT: usra v0.4s, v2.4s, #1
116+
; CHECK-NEXT: movi v2.4s, #1
117+
; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
118+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
121119
; CHECK-NEXT: ret
122120
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>
123121
%cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -298,17 +296,16 @@ define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {
298296
; CHECK-NEXT: mov w9, #9362 // =0x2492
299297
; CHECK-NEXT: movk w8, #46811, lsl #16
300298
; CHECK-NEXT: movk w9, #4681, lsl #16
301-
; CHECK-NEXT: movi v3.4s, #1
302299
; CHECK-NEXT: dup v1.4s, w8
303300
; CHECK-NEXT: dup v2.4s, w9
304301
; CHECK-NEXT: adrp x8, .LCPI11_0
305302
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
303+
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI11_0]
306304
; CHECK-NEXT: shl v0.4s, v2.4s, #31
307-
; CHECK-NEXT: ushr v1.4s, v2.4s, #1
308-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0]
309-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
310-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
311-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
305+
; CHECK-NEXT: usra v0.4s, v2.4s, #1
306+
; CHECK-NEXT: movi v2.4s, #1
307+
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
308+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
312309
; CHECK-NEXT: ret
313310
%srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
314311
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -552,17 +549,16 @@ define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {
552549
; CHECK-NEXT: mov w9, #9362 // =0x2492
553550
; CHECK-NEXT: movk w8, #46811, lsl #16
554551
; CHECK-NEXT: movk w9, #4681, lsl #16
555-
; CHECK-NEXT: movi v3.4s, #1
556552
; CHECK-NEXT: dup v1.4s, w8
557553
; CHECK-NEXT: dup v2.4s, w9
558554
; CHECK-NEXT: adrp x8, .LCPI20_0
559555
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
556+
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]
560557
; CHECK-NEXT: shl v0.4s, v2.4s, #31
561-
; CHECK-NEXT: ushr v1.4s, v2.4s, #1
562-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI20_0]
563-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
564-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
565-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
558+
; CHECK-NEXT: usra v0.4s, v2.4s, #1
559+
; CHECK-NEXT: movi v2.4s, #1
560+
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
561+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
566562
; CHECK-NEXT: ret
567563
%srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>
568564
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>

‎llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -33,18 +33,17 @@ define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {
3333
; CHECK-NEXT: mov w9, #47184 // =0xb850
3434
; CHECK-NEXT: movk w8, #49807, lsl #16
3535
; CHECK-NEXT: movk w9, #1310, lsl #16
36-
; CHECK-NEXT: movi v3.4s, #1
3736
; CHECK-NEXT: dup v1.4s, w8
3837
; CHECK-NEXT: dup v2.4s, w9
3938
; CHECK-NEXT: mov w8, #23592 // =0x5c28
4039
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
4140
; CHECK-NEXT: movk w8, #655, lsl #16
41+
; CHECK-NEXT: dup v1.4s, w8
4242
; CHECK-NEXT: shl v0.4s, v2.4s, #30
43-
; CHECK-NEXT: ushr v1.4s, v2.4s, #2
44-
; CHECK-NEXT: dup v2.4s, w8
45-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
46-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
47-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
43+
; CHECK-NEXT: usra v0.4s, v2.4s, #2
44+
; CHECK-NEXT: movi v2.4s, #1
45+
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
46+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
4847
; CHECK-NEXT: ret
4948
%srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
5049
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>
@@ -86,18 +85,17 @@ define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {
8685
; CHECK-NEXT: mov w9, #47184 // =0xb850
8786
; CHECK-NEXT: movk w8, #49807, lsl #16
8887
; CHECK-NEXT: movk w9, #1310, lsl #16
89-
; CHECK-NEXT: movi v3.4s, #1
9088
; CHECK-NEXT: dup v1.4s, w8
9189
; CHECK-NEXT: dup v2.4s, w9
9290
; CHECK-NEXT: mov w8, #23592 // =0x5c28
9391
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s
9492
; CHECK-NEXT: movk w8, #655, lsl #16
93+
; CHECK-NEXT: dup v1.4s, w8
9594
; CHECK-NEXT: shl v0.4s, v2.4s, #30
96-
; CHECK-NEXT: ushr v1.4s, v2.4s, #2
97-
; CHECK-NEXT: dup v2.4s, w8
98-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
99-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
100-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
95+
; CHECK-NEXT: usra v0.4s, v2.4s, #2
96+
; CHECK-NEXT: movi v2.4s, #1
97+
; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s
98+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
10199
; CHECK-NEXT: ret
102100
%srem = srem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
103101
%cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>

‎llvm/test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -273,16 +273,15 @@ define <4 x i32> @test_urem_even_one(<4 x i32> %X) nounwind {
273273
; CHECK: // %bb.0:
274274
; CHECK-NEXT: mov w8, #28087 // =0x6db7
275275
; CHECK-NEXT: movk w8, #46811, lsl #16
276-
; CHECK-NEXT: movi v3.4s, #1
276+
; CHECK-NEXT: movi v2.4s, #1
277277
; CHECK-NEXT: dup v1.4s, w8
278278
; CHECK-NEXT: adrp x8, .LCPI11_0
279279
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
280-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI11_0]
281280
; CHECK-NEXT: shl v1.4s, v0.4s, #31
282-
; CHECK-NEXT: ushr v0.4s, v0.4s, #1
283-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
284-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
285-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
281+
; CHECK-NEXT: usra v1.4s, v0.4s, #1
282+
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI11_0]
283+
; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
284+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
286285
; CHECK-NEXT: ret
287286
%urem = urem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>
288287
%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>

‎llvm/test/CodeGen/AArch64/urem-seteq-vec-nonzero.ll

Lines changed: 11 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -54,11 +54,10 @@ define <4 x i1> @t32_6_part0(<4 x i32> %X) nounwind {
5454
; CHECK-NEXT: mov w8, #43690 // =0xaaaa
5555
; CHECK-NEXT: movk w8, #10922, lsl #16
5656
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
57-
; CHECK-NEXT: dup v2.4s, w8
5857
; CHECK-NEXT: shl v1.4s, v0.4s, #31
59-
; CHECK-NEXT: ushr v0.4s, v0.4s, #1
60-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
61-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
58+
; CHECK-NEXT: usra v1.4s, v0.4s, #1
59+
; CHECK-NEXT: dup v0.4s, w8
60+
; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
6261
; CHECK-NEXT: xtn v0.4h, v0.4s
6362
; CHECK-NEXT: ret
6463
%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>
@@ -70,18 +69,17 @@ define <4 x i1> @t32_6_part1(<4 x i32> %X) nounwind {
7069
; CHECK-LABEL: t32_6_part1:
7170
; CHECK: // %bb.0:
7271
; CHECK-NEXT: adrp x8, .LCPI3_0
73-
; CHECK-NEXT: mov w9, #43691 // =0xaaab
74-
; CHECK-NEXT: movk w9, #43690, lsl #16
7572
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
76-
; CHECK-NEXT: adrp x8, .LCPI3_1
77-
; CHECK-NEXT: dup v2.4s, w9
73+
; CHECK-NEXT: mov w8, #43691 // =0xaaab
74+
; CHECK-NEXT: movk w8, #43690, lsl #16
7875
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
79-
; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
80-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
76+
; CHECK-NEXT: dup v1.4s, w8
77+
; CHECK-NEXT: adrp x8, .LCPI3_1
78+
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
8179
; CHECK-NEXT: shl v1.4s, v0.4s, #31
82-
; CHECK-NEXT: ushr v0.4s, v0.4s, #1
83-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
84-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
80+
; CHECK-NEXT: usra v1.4s, v0.4s, #1
81+
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_1]
82+
; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
8583
; CHECK-NEXT: xtn v0.4h, v0.4s
8684
; CHECK-NEXT: ret
8785
%urem = urem <4 x i32> %X, <i32 6, i32 6, i32 6, i32 6>

‎llvm/test/CodeGen/AArch64/urem-seteq-vec-splat.ll

Lines changed: 10 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -28,17 +28,16 @@ define <4 x i32> @test_urem_even_100(<4 x i32> %X) nounwind {
2828
; CHECK: // %bb.0:
2929
; CHECK-NEXT: mov w8, #23593 // =0x5c29
3030
; CHECK-NEXT: movk w8, #49807, lsl #16
31-
; CHECK-NEXT: movi v3.4s, #1
31+
; CHECK-NEXT: movi v2.4s, #1
3232
; CHECK-NEXT: dup v1.4s, w8
3333
; CHECK-NEXT: mov w8, #23592 // =0x5c28
3434
; CHECK-NEXT: movk w8, #655, lsl #16
3535
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
36-
; CHECK-NEXT: dup v2.4s, w8
3736
; CHECK-NEXT: shl v1.4s, v0.4s, #30
38-
; CHECK-NEXT: ushr v0.4s, v0.4s, #2
39-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
40-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
41-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
37+
; CHECK-NEXT: usra v1.4s, v0.4s, #2
38+
; CHECK-NEXT: dup v0.4s, w8
39+
; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
40+
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
4342
%urem = urem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>
@@ -72,16 +71,15 @@ define <4 x i32> @test_urem_even_neg100(<4 x i32> %X) nounwind {
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; CHECK-LABEL: test_urem_even_neg100:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adrp x8, .LCPI3_0
75-
; CHECK-NEXT: movi v3.4s, #1
74+
; CHECK-NEXT: movi v2.4s, #1
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]
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; CHECK-NEXT: adrp x8, .LCPI3_1
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; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
79-
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
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; CHECK-NEXT: shl v1.4s, v0.4s, #30
81-
; CHECK-NEXT: ushr v0.4s, v0.4s, #2
82-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
83-
; CHECK-NEXT: cmhs v0.4s, v2.4s, v0.4s
84-
; CHECK-NEXT: and v0.16b, v0.16b, v3.16b
79+
; CHECK-NEXT: usra v1.4s, v0.4s, #2
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; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI3_1]
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; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
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; CHECK-NEXT: ret
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%urem = urem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>
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%cmp = icmp eq <4 x i32> %urem, <i32 0, i32 0, i32 0, i32 0>

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