Merged main:d230bf3fce6d into amd-gfx:da5edb4170fd

Local branch amd-gfx da5edb4 Merged main:12ee3a6f53db into amd-gfx:b62921ced91f
Remote branch main d230bf3 [mlir][complex] Support Fastmath flag in the conversion of exp,expm1 (llvm#67001)

Author: SC llvm team

clang/docs/ReleaseNotes.rst

@@ -51,6 +51,8 @@ C++ Specific Potentially Breaking Changes
   parameter lists or requires-clauses. This causes mangled names to change for
   function templates in the following cases:
 
+  - When a template parameter in a function template depends on a previous
+    template parameter, such as ``template<typename T, T V> void f()``.
   - When the function has any constraints, whether from constrained template
       parameters or requires-clauses.
   - When the template parameter list includes a deduced type -- either

clang/lib/AST/TextNodeDumper.cpp

@@ -1901,8 +1901,7 @@ void TextNodeDumper::VisitFunctionDecl(const FunctionDecl *D) {
         auto Overrides = MD->overridden_methods();
         OS << "Overrides: [ ";
         dumpOverride(*Overrides.begin());
-        for (const auto *Override :
-             llvm::make_range(Overrides.begin() + 1, Overrides.end())) {
+        for (const auto *Override : llvm::drop_begin(Overrides)) {
           OS << ", ";
           dumpOverride(Override);
         }

clang/lib/Sema/SemaOpenMP.cpp

@@ -1187,9 +1187,7 @@ class DSAStackTy {
     if (!Top)
       return false;
 
-    return llvm::any_of(Top->IteratorVarDecls, [VD](const VarDecl *IteratorVD) {
-      return IteratorVD == VD->getCanonicalDecl();
-    });
+    return llvm::is_contained(Top->IteratorVarDecls, VD->getCanonicalDecl());
   }
   /// get captured field from ImplicitDefaultFirstprivateFDs
   VarDecl *getImplicitFDCapExprDecl(const FieldDecl *FD) const {

lldb/test/API/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py

@@ -1,4 +1,4 @@
-"""Test stepping over watchpoints."""
+"""Test stepping over watchpoints and instruction stepping past watchpoints."""
 
 
 import lldb
@@ -11,11 +11,25 @@ class TestStepOverWatchpoint(TestBase):
     NO_DEBUG_INFO_TESTCASE = True
 
     def get_to_start(self, bkpt_text):
-        """Test stepping over watchpoints."""
+        """Test stepping over watchpoints and instruction stepping past watchpoints.."""
         self.build()
         target, process, thread, bkpt = lldbutil.run_to_source_breakpoint(
             self, bkpt_text, lldb.SBFileSpec("main.c")
         )
+        return (target, process, thread, frame, read_watchpoint)
+
+    @add_test_categories(["basic_process"])
+    @expectedFailureAll(
+        oslist=["ios", "watchos", "tvos", "bridgeos", "macosx"],
+        archs=["aarch64", "arm"],
+        bugnumber="<rdar://problem/106868647>",
+    )
+    def test_step_over_read_watchpoint(self):
+        self.build()
+        target, process, thread, bkpt = lldbutil.run_to_source_breakpoint(
+            self, "break here for read watchpoints", lldb.SBFileSpec("main.c")
+        )
+
         frame = thread.GetFrameAtIndex(0)
         self.assertTrue(frame.IsValid(), "Failed to get frame.")
 
@@ -33,14 +47,6 @@ def get_to_start(self, bkpt_text):
         # stepping off from the breakpoint:
         bkpt.SetEnabled(False)
 
-        return (target, process, thread, frame, read_watchpoint)
-
-    # Read-write watchpoints not supported on SystemZ
-    @expectedFailureAll(archs=["s390x"])
-    @add_test_categories(["basic_process"])
-    def test_step_over(self):
-        target, process, thread, frame, wp = self.get_to_start("Set a breakpoint here")
-
         thread.StepOver()
         self.assertStopReason(
             thread.GetStopReason(),
@@ -49,39 +55,36 @@ def test_step_over(self):
         )
         self.assertEquals(thread.GetStopDescription(20), "watchpoint 1")
 
-    # Skip everywhere while modify watchpoints are sorted out.
-    @skipTestIfFn(lambda : True)
-    @expectedFailureAll(
-        oslist=["freebsd", "linux"],
-        archs=["aarch64", "arm"],
-        bugnumber="llvm.org/pr26031",
-    )
-    # Read-write watchpoints not supported on SystemZ
-    @expectedFailureAll(archs=["s390x"])
+        process.Continue()
+        self.assertState(process.GetState(), lldb.eStateStopped, PROCESS_STOPPED)
+        self.assertEquals(thread.GetStopDescription(20), "step over")
+
+        self.step_inst_for_watchpoint(1)
+
+    @add_test_categories(["basic_process"])
     @expectedFailureAll(
         oslist=["ios", "watchos", "tvos", "bridgeos", "macosx"],
         archs=["aarch64", "arm"],
-        bugnumber="<rdar://problem/34027183>",
+        bugnumber="<rdar://problem/106868647>",
     )
-    @add_test_categories(["basic_process"])
-    def test_step_instruction(self):
-        target, process, thread, frame, wp = self.get_to_start(
-            "Set breakpoint after call"
+    def test_step_over_write_watchpoint(self):
+        self.build()
+        target, process, thread, bkpt = lldbutil.run_to_source_breakpoint(
+            self, "break here for modify watchpoints", lldb.SBFileSpec("main.c")
         )
 
-        self.step_inst_for_watchpoint(1)
+        # Disable the breakpoint we hit so we don't muddy the waters with
+        # stepping off from the breakpoint:
+        bkpt.SetEnabled(False)
+
+        frame = thread.GetFrameAtIndex(0)
+        self.assertTrue(frame.IsValid(), "Failed to get frame.")
 
         write_value = frame.FindValue("g_watch_me_write", lldb.eValueTypeVariableGlobal)
         self.assertTrue(write_value, "Failed to find write value.")
 
-        # Most of the MIPS boards provide only one H/W watchpoints, and S/W
-        # watchpoints are not supported yet
-        arch = self.getArchitecture()
-        if re.match("^mips", arch) or re.match("powerpc64le", arch):
-            self.runCmd("watchpoint delete 1")
-
         error = lldb.SBError()
-        # resolve_location=True, read=False, write=True
+        # resolve_location=True, read=False, modify=True
         write_watchpoint = write_value.Watch(True, False, True, error)
         self.assertTrue(write_watchpoint, "Failed to set write watchpoint.")
         self.assertSuccess(error, "Error while setting watchpoint")
@@ -92,13 +95,13 @@ def test_step_instruction(self):
             lldb.eStopReasonWatchpoint,
             STOPPED_DUE_TO_WATCHPOINT,
         )
-        self.assertEquals(thread.GetStopDescription(20), "watchpoint 2")
+        self.assertEquals(thread.GetStopDescription(20), "watchpoint 1")
 
         process.Continue()
         self.assertState(process.GetState(), lldb.eStateStopped, PROCESS_STOPPED)
         self.assertEquals(thread.GetStopDescription(20), "step over")
 
-        self.step_inst_for_watchpoint(2)
+        self.step_inst_for_watchpoint(1)
 
     def step_inst_for_watchpoint(self, wp_id):
         watchpoint_hit = False

lldb/test/API/commands/watchpoints/step_over_watchpoint/main.c

@@ -6,14 +6,20 @@ void watch_read() {
     g_temp = g_watch_me_read;
 }
 
-void watch_write() {
-    g_watch_me_write = g_temp;
+void watch_write() { g_watch_me_write = g_temp++; }
+
+void read_watchpoint_testing() {
+  watch_read(); // break here for read watchpoints
+  g_temp = g_watch_me_read;
+}
+
+void watch_breakpoint_testing() {
+  watch_write(); // break here for modify watchpoints
+  g_watch_me_write = g_temp;
 }
 
 int main() {
-    watch_read(); // Set a breakpoint here
-    g_temp = g_watch_me_read; // Set breakpoint after call
-    watch_write();
-    g_watch_me_write = g_temp + 1;
-    return 0;
+  read_watchpoint_testing();
+  watch_breakpoint_testing();
+  return 0;
 }

llvm/include/llvm/Config/llvm-config.h.cmake

@@ -16,7 +16,7 @@
 
 /* Indicate that this is LLVM compiled from the amd-gfx branch. */
 #define LLVM_HAVE_BRANCH_AMD_GFX
-#define LLVM_MAIN_REVISION 475709
+#define LLVM_MAIN_REVISION 475719
 
 /* Define if LLVM_ENABLE_DUMP is enabled */
 #cmakedefine LLVM_ENABLE_DUMP

llvm/lib/CodeGen/GlobalISel/Utils.cpp

@@ -1173,7 +1173,7 @@ llvm::getVectorSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI) {
   if (auto Splat = getIConstantSplatSExtVal(MI, MRI))
     return RegOrConstant(*Splat);
   auto Reg = MI.getOperand(1).getReg();
-  if (any_of(make_range(MI.operands_begin() + 2, MI.operands_end()),
+  if (any_of(drop_begin(MI.operands(), 2),
              [&Reg](const MachineOperand &Op) { return Op.getReg() != Reg; }))
     return std::nullopt;
   return RegOrConstant(Reg);

llvm/lib/CodeGen/MachineCopyPropagation.cpp

@@ -1147,11 +1147,11 @@ void MachineCopyPropagation::EliminateSpillageCopies(MachineBasicBlock &MBB) {
           return;
 
         // If violate property#2, we don't fold the chain.
-        for (const MachineInstr *Spill : make_range(SC.begin() + 1, SC.end()))
+        for (const MachineInstr *Spill : drop_begin(SC))
           if (CopySourceInvalid.count(Spill))
             return;
 
-        for (const MachineInstr *Reload : make_range(RC.begin(), RC.end() - 1))
+        for (const MachineInstr *Reload : drop_end(RC))
           if (CopySourceInvalid.count(Reload))
             return;
 

llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp

@@ -516,8 +516,7 @@ static RelaxAux initRelaxAux(LinkGraph &G) {
   RelaxAux Aux;
   Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32();
   const auto &Features = G.getFeatures().getFeatures();
-  Aux.Config.HasRVC =
-      std::find(Features.begin(), Features.end(), "+c") != Features.end();
+  Aux.Config.HasRVC = llvm::is_contained(Features, "+c");
 
   for (auto &S : G.sections()) {
     if (!shouldRelax(S))

llvm/lib/IR/Instructions.cpp

@@ -130,7 +130,7 @@ Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
   // clients might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
   std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
-  copyIncomingBlocks(make_range(block_begin() + Idx + 1, block_end()), Idx);
+  copyIncomingBlocks(drop_begin(blocks(), Idx + 1), Idx);
 
   // Nuke the last value.
   Op<-1>().set(nullptr);

llvm/lib/MCA/Stages/EntryStage.cpp

@@ -67,8 +67,7 @@ llvm::Error EntryStage::cycleResume() {
 
 llvm::Error EntryStage::cycleEnd() {
   // Find the first instruction which hasn't been retired.
-  auto Range =
-      make_range(Instructions.begin() + NumRetired, Instructions.end());
+  auto Range = drop_begin(Instructions, NumRetired);
   auto It = find_if(Range, [](const std::unique_ptr<Instruction> &I) {
     return !I->isRetired();
   });

llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

@@ -1053,11 +1053,9 @@ bool AArch64ExpandPseudo::expandMultiVecPseudo(
   auto ContiguousRange = ContiguousClass.getRegisters();
   auto StridedRange = StridedClass.getRegisters();
   unsigned Opc;
-  if ((std::find(ContiguousRange.begin(), ContiguousRange.end(),
-                 Tuple.asMCReg()) != std::end(ContiguousRange))) {
+  if (llvm::is_contained(ContiguousRange, Tuple.asMCReg())) {
     Opc = ContiguousOp;
-  } else if ((std::find(StridedRange.begin(), StridedRange.end(),
-                        Tuple.asMCReg()) != std::end(StridedRange))) {
+  } else if (llvm::is_contained(StridedRange, Tuple.asMCReg())) {
     Opc = StridedOpc;
   } else
     llvm_unreachable("Cannot expand Multi-Vector pseudo");

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -5517,11 +5517,9 @@ bool AArch64InstructionSelector::tryOptBuildVecToSubregToReg(
   const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI);
   if (EltRB != DstRB)
     return false;
-  if (any_of(make_range(I.operands_begin() + 2, I.operands_end()),
-             [&MRI](const MachineOperand &Op) {
-               return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(),
-                                    MRI);
-             }))
+  if (any_of(drop_begin(I.operands(), 2), [&MRI](const MachineOperand &Op) {
+        return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), MRI);
+      }))
     return false;
   unsigned SubReg;
   const TargetRegisterClass *EltRC = getRegClassForTypeOnBank(EltTy, EltRB);

llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

@@ -1152,8 +1152,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
       if (Pred.getSUnit()->getInstr()->getOpcode() != AMDGPU::V_PERM_B32_e64)
         continue;
 
-      if (Cand &&
-          std::find(Counted.begin(), Counted.end(), Cand) != Counted.end())
+      if (Cand && llvm::is_contained(Counted, Cand))
         break;
 
       for (auto &Succ : Pred.getSUnit()->Succs) {
@@ -1174,7 +1173,7 @@ void MFMASmallGemmSingleWaveOpt::applyIGLPStrategy(
         }
 
         Cand = VMEMLookup[MI];
-        if (std::find(Counted.begin(), Counted.end(), Cand) != Counted.end()) {
+        if (llvm::is_contained(Counted, Cand)) {
           MissedAny = true;
           break;
         }

llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp

@@ -355,9 +355,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
         int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
         assert(MFI.getStackID(FI) == TargetStackID::SGPRSpill);
 
-        bool IsCalleeSaveSGPRSpill =
-            std::find(CalleeSavedFIs.begin(), CalleeSavedFIs.end(), FI) !=
-            CalleeSavedFIs.end();
+        bool IsCalleeSaveSGPRSpill = llvm::is_contained(CalleeSavedFIs, FI);
         if (IsCalleeSaveSGPRSpill) {
           // Spill callee-saved SGPRs into physical VGPR lanes.
 

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -228,9 +228,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     MI.setDesc(TII.get(TargetOpcode::COPY));
     return true;
   case TargetOpcode::G_CONSTANT:
-    if (!selectConstant(MI, MIB, MRI))
-      return false;
-    break;
+    return selectConstant(MI, MIB, MRI);
   case TargetOpcode::G_BRCOND: {
     // TODO: Fold with G_ICMP.
     auto Bcc =
@@ -242,10 +240,6 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
   default:
     return false;
   }
-
-  MI.eraseFromParent();
-
-  return true;
 }
 
 void RISCVInstructionSelector::renderNegImm(MachineInstrBuilder &MIB,
@@ -312,6 +306,13 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
   Register FinalReg = MI.getOperand(0).getReg();
   int64_t Imm = MI.getOperand(1).getCImm()->getSExtValue();
 
+  if (Imm == 0) {
+    MI.getOperand(1).ChangeToRegister(RISCV::X0, false);
+    RBI.constrainGenericRegister(FinalReg, RISCV::GPRRegClass, MRI);
+    MI.setDesc(TII.get(TargetOpcode::COPY));
+    return true;
+  }
+
   RISCVMatInt::InstSeq Seq =
       RISCVMatInt::generateInstSeq(Imm, Subtarget->getFeatureBits());
   unsigned NumInsts = Seq.size();
@@ -358,6 +359,7 @@ bool RISCVInstructionSelector::selectConstant(MachineInstr &MI,
     SrcReg = DstReg;
   }
 
+  MI.eraseFromParent();
   return true;
 }
 

llvm/lib/Transforms/Scalar/SROA.cpp

@@ -3126,8 +3126,7 @@ class llvm::sroa::AllocaSliceRewriter
       if (IsDest) {
         // Update the address component of linked dbg.assigns.
         for (auto *DAI : at::getAssignmentMarkers(&II)) {
-          if (any_of(DAI->location_ops(),
-                     [&](Value *V) { return V == II.getDest(); }) ||
+          if (llvm::is_contained(DAI->location_ops(), II.getDest()) ||
               DAI->getAddress() == II.getDest())
             DAI->replaceVariableLocationOp(II.getDest(), AdjustedPtr);
         }