Skip to content

Commit d76d5c7

Browse files
committed
[RISCV] Sink more common code from RVInst/RVInst16 into RVInstCommon. NFC
Reviewed By: wangpc Differential Revision: https://reviews.llvm.org/D155787
1 parent 845b03c commit d76d5c7

File tree

2 files changed

+9
-13
lines changed

2 files changed

+9
-13
lines changed

llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -156,9 +156,15 @@ def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
156156
def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>;
157157
def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
158158

159-
class RVInstCommon<InstFormat format> : Instruction {
159+
class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
160+
list<dag> pattern, InstFormat format> : Instruction {
160161
let Namespace = "RISCV";
161162

163+
dag OutOperandList = outs;
164+
dag InOperandList = ins;
165+
let AsmString = opcodestr # "\t" # argstr;
166+
let Pattern = pattern;
167+
162168
let TSFlags{4-0} = format.Value;
163169

164170
// Defaults
@@ -210,7 +216,7 @@ class RVInstCommon<InstFormat format> : Instruction {
210216

211217
class RVInst<dag outs, dag ins, string opcodestr, string argstr,
212218
list<dag> pattern, InstFormat format>
213-
: RVInstCommon<format> {
219+
: RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
214220
field bits<32> Inst;
215221
// SoftFail is a field the disassembler can use to provide a way for
216222
// instructions to not match without killing the whole decode process. It is
@@ -222,11 +228,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
222228
bits<7> Opcode = 0;
223229

224230
let Inst{6-0} = Opcode;
225-
226-
dag OutOperandList = outs;
227-
dag InOperandList = ins;
228-
let AsmString = opcodestr # "\t" # argstr;
229-
let Pattern = pattern;
230231
}
231232

232233
// Pseudo instructions

llvm/lib/Target/RISCV/RISCVInstrFormatsC.td

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212

1313
class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
1414
list<dag> pattern, InstFormat format>
15-
: RVInstCommon<format> {
15+
: RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
1616
field bits<16> Inst;
1717
// SoftFail is a field the disassembler can use to provide a way for
1818
// instructions to not match without killing the whole decode process. It is
@@ -22,11 +22,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
2222
let Size = 2;
2323

2424
bits<2> Opcode = 0;
25-
26-
dag OutOperandList = outs;
27-
dag InOperandList = ins;
28-
let AsmString = opcodestr # "\t" # argstr;
29-
let Pattern = pattern;
3025
}
3126

3227
class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,

0 commit comments

Comments
 (0)