@@ -156,9 +156,15 @@ def OPC_SYSTEM : RISCVOpcode<"SYSTEM", 0b1110011>;
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def OPC_OP_P : RISCVOpcode<"OP_P", 0b1110111>;
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def OPC_CUSTOM_3 : RISCVOpcode<"CUSTOM_3", 0b1111011>;
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- class RVInstCommon<InstFormat format> : Instruction {
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+ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
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+ list<dag> pattern, InstFormat format> : Instruction {
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let Namespace = "RISCV";
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+ dag OutOperandList = outs;
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+ dag InOperandList = ins;
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+ let AsmString = opcodestr # "\t" # argstr;
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+ let Pattern = pattern;
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+
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let TSFlags{4-0} = format.Value;
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// Defaults
@@ -210,7 +216,7 @@ class RVInstCommon<InstFormat format> : Instruction {
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class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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list<dag> pattern, InstFormat format>
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- : RVInstCommon<format> {
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+ : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
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field bits<32> Inst;
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// SoftFail is a field the disassembler can use to provide a way for
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// instructions to not match without killing the whole decode process. It is
@@ -222,11 +228,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
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bits<7> Opcode = 0;
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let Inst{6-0} = Opcode;
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-
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- dag OutOperandList = outs;
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- dag InOperandList = ins;
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- let AsmString = opcodestr # "\t" # argstr;
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- let Pattern = pattern;
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}
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// Pseudo instructions
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