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[NFC][X86] Clang-format X86RecognizableInstr.h (llvm#73279)
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‎llvm/utils/TableGen/X86RecognizableInstr.h

Lines changed: 151 additions & 144 deletions
Original file line numberDiff line numberDiff line change
@@ -25,144 +25,157 @@
2525
struct InstructionSpecifier;
2626

2727
namespace llvm {
28-
2928
class Record;
30-
31-
#define X86_INSTR_MRM_MAPPING \
32-
MAP(C0, 64) \
33-
MAP(C1, 65) \
34-
MAP(C2, 66) \
35-
MAP(C3, 67) \
36-
MAP(C4, 68) \
37-
MAP(C5, 69) \
38-
MAP(C6, 70) \
39-
MAP(C7, 71) \
40-
MAP(C8, 72) \
41-
MAP(C9, 73) \
42-
MAP(CA, 74) \
43-
MAP(CB, 75) \
44-
MAP(CC, 76) \
45-
MAP(CD, 77) \
46-
MAP(CE, 78) \
47-
MAP(CF, 79) \
48-
MAP(D0, 80) \
49-
MAP(D1, 81) \
50-
MAP(D2, 82) \
51-
MAP(D3, 83) \
52-
MAP(D4, 84) \
53-
MAP(D5, 85) \
54-
MAP(D6, 86) \
55-
MAP(D7, 87) \
56-
MAP(D8, 88) \
57-
MAP(D9, 89) \
58-
MAP(DA, 90) \
59-
MAP(DB, 91) \
60-
MAP(DC, 92) \
61-
MAP(DD, 93) \
62-
MAP(DE, 94) \
63-
MAP(DF, 95) \
64-
MAP(E0, 96) \
65-
MAP(E1, 97) \
66-
MAP(E2, 98) \
67-
MAP(E3, 99) \
68-
MAP(E4, 100) \
69-
MAP(E5, 101) \
70-
MAP(E6, 102) \
71-
MAP(E7, 103) \
72-
MAP(E8, 104) \
73-
MAP(E9, 105) \
74-
MAP(EA, 106) \
75-
MAP(EB, 107) \
76-
MAP(EC, 108) \
77-
MAP(ED, 109) \
78-
MAP(EE, 110) \
79-
MAP(EF, 111) \
80-
MAP(F0, 112) \
81-
MAP(F1, 113) \
82-
MAP(F2, 114) \
83-
MAP(F3, 115) \
84-
MAP(F4, 116) \
85-
MAP(F5, 117) \
86-
MAP(F6, 118) \
87-
MAP(F7, 119) \
88-
MAP(F8, 120) \
89-
MAP(F9, 121) \
90-
MAP(FA, 122) \
91-
MAP(FB, 123) \
92-
MAP(FC, 124) \
93-
MAP(FD, 125) \
94-
MAP(FE, 126) \
29+
#define X86_INSTR_MRM_MAPPING \
30+
MAP(C0, 64) \
31+
MAP(C1, 65) \
32+
MAP(C2, 66) \
33+
MAP(C3, 67) \
34+
MAP(C4, 68) \
35+
MAP(C5, 69) \
36+
MAP(C6, 70) \
37+
MAP(C7, 71) \
38+
MAP(C8, 72) \
39+
MAP(C9, 73) \
40+
MAP(CA, 74) \
41+
MAP(CB, 75) \
42+
MAP(CC, 76) \
43+
MAP(CD, 77) \
44+
MAP(CE, 78) \
45+
MAP(CF, 79) \
46+
MAP(D0, 80) \
47+
MAP(D1, 81) \
48+
MAP(D2, 82) \
49+
MAP(D3, 83) \
50+
MAP(D4, 84) \
51+
MAP(D5, 85) \
52+
MAP(D6, 86) \
53+
MAP(D7, 87) \
54+
MAP(D8, 88) \
55+
MAP(D9, 89) \
56+
MAP(DA, 90) \
57+
MAP(DB, 91) \
58+
MAP(DC, 92) \
59+
MAP(DD, 93) \
60+
MAP(DE, 94) \
61+
MAP(DF, 95) \
62+
MAP(E0, 96) \
63+
MAP(E1, 97) \
64+
MAP(E2, 98) \
65+
MAP(E3, 99) \
66+
MAP(E4, 100) \
67+
MAP(E5, 101) \
68+
MAP(E6, 102) \
69+
MAP(E7, 103) \
70+
MAP(E8, 104) \
71+
MAP(E9, 105) \
72+
MAP(EA, 106) \
73+
MAP(EB, 107) \
74+
MAP(EC, 108) \
75+
MAP(ED, 109) \
76+
MAP(EE, 110) \
77+
MAP(EF, 111) \
78+
MAP(F0, 112) \
79+
MAP(F1, 113) \
80+
MAP(F2, 114) \
81+
MAP(F3, 115) \
82+
MAP(F4, 116) \
83+
MAP(F5, 117) \
84+
MAP(F6, 118) \
85+
MAP(F7, 119) \
86+
MAP(F8, 120) \
87+
MAP(F9, 121) \
88+
MAP(FA, 122) \
89+
MAP(FB, 123) \
90+
MAP(FC, 124) \
91+
MAP(FD, 125) \
92+
MAP(FE, 126) \
9593
MAP(FF, 127)
9694

9795
// A clone of X86 since we can't depend on something that is generated.
9896
namespace X86Local {
99-
enum {
100-
Pseudo = 0,
101-
RawFrm = 1,
102-
AddRegFrm = 2,
103-
RawFrmMemOffs = 3,
104-
RawFrmSrc = 4,
105-
RawFrmDst = 5,
106-
RawFrmDstSrc = 6,
107-
RawFrmImm8 = 7,
108-
RawFrmImm16 = 8,
109-
AddCCFrm = 9,
110-
PrefixByte = 10,
111-
MRMDestMem4VOp3CC = 20,
112-
MRMr0 = 21,
113-
MRMSrcMemFSIB = 22,
114-
MRMDestMemFSIB = 23,
115-
MRMDestMem = 24,
116-
MRMSrcMem = 25,
117-
MRMSrcMem4VOp3 = 26,
118-
MRMSrcMemOp4 = 27,
119-
MRMSrcMemCC = 28,
120-
MRMXmCC = 30, MRMXm = 31,
121-
MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35,
122-
MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39,
123-
MRMDestReg = 40,
124-
MRMSrcReg = 41,
125-
MRMSrcReg4VOp3 = 42,
126-
MRMSrcRegOp4 = 43,
127-
MRMSrcRegCC = 44,
128-
MRMXrCC = 46, MRMXr = 47,
129-
MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51,
130-
MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55,
131-
MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59,
132-
MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63,
97+
enum {
98+
Pseudo = 0,
99+
RawFrm = 1,
100+
AddRegFrm = 2,
101+
RawFrmMemOffs = 3,
102+
RawFrmSrc = 4,
103+
RawFrmDst = 5,
104+
RawFrmDstSrc = 6,
105+
RawFrmImm8 = 7,
106+
RawFrmImm16 = 8,
107+
AddCCFrm = 9,
108+
PrefixByte = 10,
109+
MRMDestMem4VOp3CC = 20,
110+
MRMr0 = 21,
111+
MRMSrcMemFSIB = 22,
112+
MRMDestMemFSIB = 23,
113+
MRMDestMem = 24,
114+
MRMSrcMem = 25,
115+
MRMSrcMem4VOp3 = 26,
116+
MRMSrcMemOp4 = 27,
117+
MRMSrcMemCC = 28,
118+
MRMXmCC = 30,
119+
MRMXm = 31,
120+
MRM0m = 32,
121+
MRM1m = 33,
122+
MRM2m = 34,
123+
MRM3m = 35,
124+
MRM4m = 36,
125+
MRM5m = 37,
126+
MRM6m = 38,
127+
MRM7m = 39,
128+
MRMDestReg = 40,
129+
MRMSrcReg = 41,
130+
MRMSrcReg4VOp3 = 42,
131+
MRMSrcRegOp4 = 43,
132+
MRMSrcRegCC = 44,
133+
MRMXrCC = 46,
134+
MRMXr = 47,
135+
MRM0r = 48,
136+
MRM1r = 49,
137+
MRM2r = 50,
138+
MRM3r = 51,
139+
MRM4r = 52,
140+
MRM5r = 53,
141+
MRM6r = 54,
142+
MRM7r = 55,
143+
MRM0X = 56,
144+
MRM1X = 57,
145+
MRM2X = 58,
146+
MRM3X = 59,
147+
MRM4X = 60,
148+
MRM5X = 61,
149+
MRM6X = 62,
150+
MRM7X = 63,
133151
#define MAP(from, to) MRM_##from = to,
134-
X86_INSTR_MRM_MAPPING
152+
X86_INSTR_MRM_MAPPING
135153
#undef MAP
136-
};
137-
138-
enum {
139-
OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7,
140-
T_MAP5 = 8, T_MAP6 = 9, T_MAP7 = 10
141-
};
142-
143-
enum {
144-
PD = 1, XS = 2, XD = 3, PS = 4
145-
};
146-
147-
enum {
148-
VEX = 1, XOP = 2, EVEX = 3
149-
};
150-
151-
enum {
152-
OpSize16 = 1, OpSize32 = 2
153-
};
154+
};
154155

155-
enum {
156-
AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
157-
};
156+
enum {
157+
OB = 0,
158+
TB = 1,
159+
T8 = 2,
160+
TA = 3,
161+
XOP8 = 4,
162+
XOP9 = 5,
163+
XOPA = 6,
164+
ThreeDNow = 7,
165+
T_MAP5 = 8,
166+
T_MAP6 = 9,
167+
T_MAP7 = 10
168+
};
158169

159-
enum { ExplicitREX2 = 1 };
160-
}
170+
enum { PD = 1, XS = 2, XD = 3, PS = 4 };
171+
enum { VEX = 1, XOP = 2, EVEX = 3 };
172+
enum { OpSize16 = 1, OpSize32 = 2 };
173+
enum { AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 };
174+
enum { ExplicitREX2 = 1 };
175+
} // namespace X86Local
161176

162177
namespace X86Disassembler {
163-
164178
class DisassemblerTables;
165-
166179
/// Extract common fields of a single X86 instruction from a CodeGenInstruction
167180
struct RecognizableInstrBase {
168181
/// The OpPrefix field from the record
@@ -223,7 +236,7 @@ struct RecognizableInstrBase {
223236
class RecognizableInstr : public RecognizableInstrBase {
224237
private:
225238
/// The record from the .td files corresponding to this instruction
226-
const Record* Rec;
239+
const Record *Rec;
227240
/// The instruction name as listed in the tables
228241
std::string Name;
229242
// Whether the instruction has the predicate "In32BitMode"
@@ -233,13 +246,13 @@ class RecognizableInstr : public RecognizableInstrBase {
233246
/// The operands of the instruction, as listed in the CodeGenInstruction.
234247
/// They are not one-to-one with operands listed in the MCInst; for example,
235248
/// memory operands expand to 5 operands in the MCInst
236-
const std::vector<CGIOperandList::OperandInfo>* Operands;
249+
const std::vector<CGIOperandList::OperandInfo> *Operands;
237250

238251
/// The opcode of the instruction, as used in an MCInst
239252
InstrUID UID;
240253
/// The description of the instruction that is emitted into the instruction
241254
/// info table
242-
InstructionSpecifier* Spec;
255+
InstructionSpecifier *Spec;
243256

244257
/// insnContext - Returns the primary context in which the instruction is
245258
/// valid.
@@ -259,8 +272,8 @@ class RecognizableInstr : public RecognizableInstrBase {
259272
/// If register size does not match OpSize, then
260273
/// register sizes keep their size.
261274
/// @return - The operand's type.
262-
static OperandType typeFromString(const std::string& s,
263-
bool hasREX_W, uint8_t OpSize);
275+
static OperandType typeFromString(const std::string &s, bool hasREX_W,
276+
uint8_t OpSize);
264277

265278
/// immediateEncodingFromString - Translates an immediate encoding from the
266279
/// string provided in the LLVM tables to an OperandEncoding for use in
@@ -290,8 +303,8 @@ class RecognizableInstr : public RecognizableInstrBase {
290303
uint8_t OpSize);
291304
static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
292305
uint8_t OpSize);
293-
static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
294-
uint8_t OpSize);
306+
static OperandEncoding
307+
writemaskRegisterEncodingFromString(const std::string &s, uint8_t OpSize);
295308

296309
/// Adjust the encoding type for an operand based on the instruction.
297310
void adjustOperandEncoding(OperandEncoding &encoding);
@@ -314,14 +327,12 @@ class RecognizableInstr : public RecognizableInstrBase {
314327
/// @param operandMapping - The operand mapping, which has an entry for
315328
/// each operand that indicates whether it is a
316329
/// duplicate, and of what.
317-
void handleOperand(bool optional,
318-
unsigned &operandIndex,
330+
void handleOperand(bool optional, unsigned &operandIndex,
319331
unsigned &physicalOperandIndex,
320332
unsigned numPhysicalOperands,
321333
const unsigned *operandMapping,
322-
OperandEncoding (*encodingFromString)
323-
(const std::string&,
324-
uint8_t OpSize));
334+
OperandEncoding (*encodingFromString)(const std::string &,
335+
uint8_t OpSize));
325336

326337
/// emitInstructionSpecifier - Loads the instruction specifier for the current
327338
/// instruction into a DisassemblerTables.
@@ -342,8 +353,7 @@ class RecognizableInstr : public RecognizableInstrBase {
342353
/// \param tables The DisassemblerTables that the specifier will be added to.
343354
/// \param insn The CodeGenInstruction to extract information from.
344355
/// \param uid The unique ID of the current instruction.
345-
RecognizableInstr(DisassemblerTables &tables,
346-
const CodeGenInstruction &insn,
356+
RecognizableInstr(DisassemblerTables &tables, const CodeGenInstruction &insn,
347357
InstrUID uid);
348358
/// processInstr - Accepts a CodeGenInstruction and loads decode information
349359
/// for it into a DisassemblerTables if appropriate.
@@ -354,8 +364,7 @@ class RecognizableInstr : public RecognizableInstrBase {
354364
/// information.
355365
/// \param uid The unique ID of the instruction.
356366
static void processInstr(DisassemblerTables &tables,
357-
const CodeGenInstruction &insn,
358-
InstrUID uid);
367+
const CodeGenInstruction &insn, InstrUID uid);
359368
};
360369

361370
std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant);
@@ -365,7 +374,5 @@ bool isImmediateOperand(const Record *Rec);
365374
unsigned getRegOperandSize(const Record *RegRec);
366375
unsigned getMemOperandSize(const Record *MemRec);
367376
} // namespace X86Disassembler
368-
369377
} // namespace llvm
370-
371378
#endif

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