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[llvm][AArch64][Assembly]: Add FDOT2/FDOT4 assembly and disassembly. (llvm#70237)
This patch adds the feature flag FDOT2/FDOT4 and the assembly/disassembly for the following instructions of NEON and SVE2: * NEON: - FDOTlane - FDOT * SVE2: - FDOT_ZZZI_BtoH - FDOT_ZZZ_BtoH - FDOT_ZZZI_BtoS - FDOT_ZZZ_BtoS That is according to this documentation: https://developer.arm.com/documentation/ddi0602/2023-09
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‎llvm/include/llvm/TargetParser/AArch64TargetParser.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -164,6 +164,10 @@ enum ArchExtKind : unsigned {
164164
AEK_FAMINMAX = 60, // FEAT_FAMINMAX
165165
AEK_FP8FMA = 61, // FEAT_FP8FMA
166166
AEK_SSVE_FP8FMA = 62, // FEAT_SSVE_FP8FMA
167+
AEK_FP8DOT2 = 63, // FEAT_FP8DOT2
168+
AEK_SSVE_FP8DOT2 = 64, // FEAT_SSVE_FP8DOT2
169+
AEK_FP8DOT4 = 65, // FEAT_FP8DOT4
170+
AEK_SSVE_FP8DOT4 = 66, // FEAT_SSVE_FP8DOT4
167171
AEK_NUM_EXTENSIONS
168172
};
169173
using ExtensionBitset = Bitset<AEK_NUM_EXTENSIONS>;
@@ -277,6 +281,10 @@ inline constexpr ExtensionInfo Extensions[] = {
277281
{"faminmax", AArch64::AEK_FAMINMAX, "+faminmax", "-faminmax", FEAT_INIT, "", 0},
278282
{"fp8fma", AArch64::AEK_FP8FMA, "+fp8fma", "-fp8fma", FEAT_INIT, "+fpmr", 0},
279283
{"ssve-fp8fma", AArch64::AEK_SSVE_FP8FMA, "+ssve-fp8fma", "-ssve-fp8fma", FEAT_INIT, "+sme2", 0},
284+
{"fp8dot2", AArch64::AEK_FP8DOT2, "+fp8dot2", "-fp8dot2", FEAT_INIT, "", 0},
285+
{"ssve-fp8dot2", AArch64::AEK_SSVE_FP8DOT2, "+ssve-fp8dot2", "-ssve-fp8dot2", FEAT_INIT, "+sme2", 0},
286+
{"fp8dot4", AArch64::AEK_FP8DOT4, "+fp8dot4", "-fp8dot4", FEAT_INIT, "", 0},
287+
{"ssve-fp8dot4", AArch64::AEK_SSVE_FP8DOT4, "+ssve-fp8dot4", "-ssve-fp8dot4", FEAT_INIT, "+sme2", 0},
280288
// Special cases
281289
{"none", AArch64::AEK_NONE, {}, {}, FEAT_INIT, "", ExtensionInfo::MaxFMVPriority},
282290
};

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -523,6 +523,18 @@ def FeatureFP8FMA : SubtargetFeature<"fp8fma", "HasFP8FMA", "true",
523523
def FeatureSSVE_FP8FMA : SubtargetFeature<"ssve-fp8fma", "HasSSVE_FP8FMA", "true",
524524
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>;
525525

526+
def FeatureFP8DOT2: SubtargetFeature<"fp8dot2", "HasFP8DOT2", "true",
527+
"Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">;
528+
529+
def FeatureSSVE_FP8DOT2 : SubtargetFeature<"ssve-fp8dot2", "HasSSVE_FP8DOT2", "true",
530+
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>;
531+
532+
def FeatureFP8DOT4: SubtargetFeature<"fp8dot4", "HasFP8DOT4", "true",
533+
"Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">;
534+
535+
def FeatureSSVE_FP8DOT4 : SubtargetFeature<"ssve-fp8dot4", "HasSSVE_FP8DOT4", "true",
536+
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>;
537+
526538
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
527539
"Apple A7 (the CPU formerly known as Cyclone)">;
528540

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 37 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6108,6 +6108,21 @@ multiclass SIMDThreeVectorCvt<string asm> {
61086108
V128, v16i8, v4f32, null_frag>;
61096109
}
61106110

6111+
// TODO: Create a new Value Type v8f8 and v16f8
6112+
multiclass SIMDThreeSameVectorDOT2<string asm> {
6113+
def v4f16 : BaseSIMDThreeSameVectorDot<0b0, 0b0, 0b01, 0b1111, asm, ".4h", ".8b",
6114+
V64, v4f16, v8i8, null_frag>;
6115+
def v8f16 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b01, 0b1111, asm, ".8h", ".16b",
6116+
V128, v8f16, v16i8, null_frag>;
6117+
}
6118+
6119+
multiclass SIMDThreeSameVectorDOT4<string asm> {
6120+
def v2f32 : BaseSIMDThreeSameVectorDot<0b0, 0b0, 0b00, 0b1111, asm, ".2s", ".8b",
6121+
V64, v2f32, v8i8, null_frag>;
6122+
def v4f32 : BaseSIMDThreeSameVectorDot<0b1, 0b0, 0b00, 0b1111, asm, ".4s", ".16b",
6123+
V128, v4f32, v16i8, null_frag>;
6124+
}
6125+
61116126
//----------------------------------------------------------------------------
61126127
// AdvSIMD two register vector instructions.
61136128
//----------------------------------------------------------------------------
@@ -8570,10 +8585,10 @@ class SIMDThreeSameVectorMatMul<bit B, bit U, string asm, SDPatternOperator OpNo
85708585
//----------------------------------------------------------------------------
85718586
// ARMv8.2-A Dot Product Instructions (Indexed)
85728587
class BaseSIMDThreeSameVectorIndexS<bit Q, bit U, bits<2> size, bits<4> opc, string asm,
8573-
string dst_kind, string lhs_kind, string rhs_kind,
8574-
RegisterOperand RegType,
8575-
ValueType AccumType, ValueType InputType,
8576-
SDPatternOperator OpNode> :
8588+
string dst_kind, string lhs_kind, string rhs_kind,
8589+
RegisterOperand RegType,
8590+
ValueType AccumType, ValueType InputType,
8591+
SDPatternOperator OpNode> :
85778592
BaseSIMDIndexedTied<Q, U, 0b0, size, opc, RegType, RegType, V128,
85788593
VectorIndexS, asm, "", dst_kind, lhs_kind, rhs_kind,
85798594
[(set (AccumType RegType:$dst),
@@ -8595,6 +8610,14 @@ multiclass SIMDThreeSameVectorDotIndex<bit U, bit Mixed, bits<2> size, string as
85958610
V128, v4i32, v16i8, OpNode>;
85968611
}
85978612

8613+
// TODO: The vectors v8i8 and v16i8 should be v8f8 and v16f8
8614+
multiclass SIMDThreeSameVectorFP8DOT4Index<string asm> {
8615+
def v8f8 : BaseSIMDThreeSameVectorIndexS<0b0, 0b0, 0b00, 0b0000, asm, ".2s", ".8b", ".4b",
8616+
V64, v2f32, v8i8, null_frag>;
8617+
def v16f8 : BaseSIMDThreeSameVectorIndexS<0b1, 0b0, 0b00, 0b0000, asm, ".4s", ".16b",".4b",
8618+
V128, v4f32, v16i8, null_frag>;
8619+
}
8620+
85988621
// ARMv8.2-A Fused Multiply Add-Long Instructions (Indexed)
85998622
let mayRaiseFPException = 1, Uses = [FPCR] in
86008623
class BaseSIMDThreeSameVectorIndexH<bit Q, bit U, bits<2> sz, bits<4> opc, string asm,
@@ -8624,6 +8647,16 @@ multiclass SIMDThreeSameVectorFMLIndex<bit U, bits<4> opc, string asm,
86248647
V128, V128_lo, v4f32, v8f16, OpNode>;
86258648
}
86268649

8650+
//----------------------------------------------------------------------------
8651+
// FP8 Advanced SIMD vector x indexed element
8652+
// TODO: Replace value types v8i8 and v16i8 by v8f8 and v16f8
8653+
multiclass SIMDThreeSameVectorFP8DOT2Index<string asm> {
8654+
def v4f16 : BaseSIMDThreeSameVectorIndexH<0b0, 0b0, 0b01, 0b0000, asm, ".4h", ".8b", ".2b",
8655+
V64, V128_lo, v4f16, v8i8, null_frag>;
8656+
def v8f16 : BaseSIMDThreeSameVectorIndexH<0b1, 0b0, 0b01, 0b0000, asm, ".8h", ".16b", ".2b",
8657+
V128, V128_lo, v8f16, v8i16, null_frag>;
8658+
}
8659+
86278660
multiclass SIMDFPIndexed<bit U, bits<4> opc, string asm,
86288661
SDPatternOperator OpNode> {
86298662
let mayRaiseFPException = 1, Uses = [FPCR] in {

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,20 @@ def HasSSVE_FP8FMA : Predicate<"Subtarget->SSVE_FP8FMA() || "
173173
AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8FMA,
174174
(all_of FeatureSVE2, FeatureFP8FMA)),
175175
"ssve-fp8fma or (sve2 and fp8fma)">;
176+
def HasFP8DOT2 : Predicate<"Subtarget->hasFP8DOT2()">,
177+
AssemblerPredicateWithAll<(all_of FeatureFP8DOT2), "fp8dot2">;
178+
def HasSSVE_FP8DOT2 : Predicate<"Subtarget->hasSSVE_FP8DOT2() || "
179+
"(Subtarget->hasSVE2() && Subtarget->hasFP8DOT2())">,
180+
AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8DOT2,
181+
(all_of FeatureSVE2, FeatureFP8DOT2)),
182+
"ssve-fp8dot2 or (sve2 and fp8dot2)">;
183+
def HasFP8DOT4 : Predicate<"Subtarget->hasFP8DOT4()">,
184+
AssemblerPredicateWithAll<(all_of FeatureFP8DOT4), "fp8dot4">;
185+
def HasSSVE_FP8DOT4 : Predicate<"Subtarget->hasSSVE_FP8DOT4() || "
186+
"(Subtarget->hasSVE2() && Subtarget->hasFP8DOT4())">,
187+
AssemblerPredicateWithAll<(any_of FeatureSSVE_FP8DOT4,
188+
(all_of FeatureSVE2, FeatureFP8DOT4)),
189+
"ssve-fp8dot4 or (sve2 and fp8dot4)">;
176190

177191
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
178192
// they should be enabled if either has been specified.
@@ -9309,6 +9323,16 @@ let Predicates = [HasFP8FMA] in {
93099323
defm FMLALLTT : SIMDThreeSameVectorMLAL<0b1, 0b01, "fmlalltt">;
93109324
} // End let Predicates = [HasFP8FMA]
93119325

9326+
let Predicates = [HasFP8DOT2] in {
9327+
defm FDOTlane : SIMDThreeSameVectorFP8DOT2Index<"fdot">;
9328+
defm FDOT : SIMDThreeSameVectorDOT2<"fdot">;
9329+
} // End let Predicates = [HasFP8DOT2]
9330+
9331+
let Predicates = [HasFP8DOT4] in {
9332+
defm FDOTlane : SIMDThreeSameVectorFP8DOT4Index<"fdot">;
9333+
defm FDOT : SIMDThreeSameVectorDOT4<"fdot">;
9334+
} // End let Predicates = [HasFP8DOT4]
9335+
93129336
include "AArch64InstrAtomics.td"
93139337
include "AArch64SVEInstrInfo.td"
93149338
include "AArch64SMEInstrInfo.td"

‎llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4064,3 +4064,20 @@ def FMLALLBT_ZZZ : sve2_fp8_mla<0b001, ZPR32, "fmlallbt">;
40644064
def FMLALLTB_ZZZ : sve2_fp8_mla<0b010, ZPR32, "fmlalltb">;
40654065
def FMLALLTT_ZZZ : sve2_fp8_mla<0b011, ZPR32, "fmlalltt">;
40664066
} // End HasSSVE_FP8FMA
4067+
4068+
let Predicates = [HasSSVE_FP8DOT2] in {
4069+
// FP8 Widening Dot-Product - Indexed Group
4070+
defm FDOT_ZZZI_BtoH : sve2_fp8_dot_indexed<"fdot">;
4071+
// FP8 Widening Dot-Product - Group
4072+
// TODO: Replace nxv16i8 by nxv16f8
4073+
defm FDOT_ZZZ_BtoH : sve_float_dot<0b0, 0b1, ZPR16, ZPR8, "fdot", nxv16i8, null_frag>;
4074+
}
4075+
4076+
// TODO: Replace nxv16i8 by nxv16f8
4077+
let Predicates = [HasSSVE_FP8DOT4] in {
4078+
// FP8 Widening Dot-Product - Indexed Group
4079+
defm FDOT_ZZZI_BtoS : sve_float_dot_indexed<0b1, 0b01, ZPR8, ZPR3b8, "fdot",
4080+
nxv16i8, null_frag>;
4081+
// FP8 Widening Dot-Product - Group
4082+
defm FDOT_ZZZ_BtoS : sve_float_dot<0b1, 0b1, ZPR32, ZPR8, "fdot", nxv16i8, null_frag>;
4083+
}

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3654,6 +3654,10 @@ static const struct Extension {
36543654
{"faminmax", {AArch64::FeatureFAMINMAX}},
36553655
{"fp8fma", {AArch64::FeatureFP8FMA}},
36563656
{"ssve-fp8fma", {AArch64::FeatureSSVE_FP8FMA}},
3657+
{"fp8dot2", {AArch64::FeatureFP8DOT2}},
3658+
{"ssve-fp8dot2", {AArch64::FeatureSSVE_FP8DOT2}},
3659+
{"fp8dot4", {AArch64::FeatureFP8DOT4}},
3660+
{"ssve-fp8dot4", {AArch64::FeatureSSVE_FP8DOT4}},
36573661
};
36583662

36593663
static void setRequiredFeatureString(FeatureBitset FBS, std::string &Str) {

‎llvm/lib/Target/AArch64/SVEInstrFormats.td

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10193,3 +10193,13 @@ class sve2_fp8_mla_long_long_by_indexed_elem<bits<2> TT, string mnemonic>
1019310193
let DestructiveInstType = DestructiveOther;
1019410194
let ElementSize = ZPR32.ElementSize;
1019510195
}
10196+
10197+
// FP8 Widening Dot-Product - Indexed Group
10198+
multiclass sve2_fp8_dot_indexed<string mnemonic>{
10199+
def NAME : sve_float_dot_indexed<0b0, ZPR16, ZPR8, ZPR3b8, VectorIndexH, mnemonic> {
10200+
bits<3> iop;
10201+
let Inst{20-19} = iop{2-1};
10202+
let Inst{11} = iop{0};
10203+
let Inst{10} = 0b1;
10204+
}
10205+
}

‎llvm/test/MC/AArch64/FP8/directive-arch-negative.s

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,3 +23,15 @@ fmlalb v0.8h, v0.16b, v0.16b
2323
fmlalb z23.h, z13.b, z0.b[7]
2424
// CHECK: error: instruction requires: ssve-fp8fma or (sve2 and fp8fma)
2525
// CHECK: fmlalb z23.h, z13.b, z0.b[7]
26+
27+
.arch armv9-a+fp8dot2
28+
.arch armv9-a+nofp8dot2
29+
fdot v31.4h, v0.8b, v0.8b
30+
// CHECK: error: instruction requires: fp8dot2
31+
// CHECK: fdot v31.4h, v0.8b, v0.8b
32+
33+
.arch armv9-a+fp8dot4
34+
.arch armv9-a+nofp8dot4
35+
fdot v0.2s, v0.8b, v31.8b
36+
// CHECK: error: instruction requires: fp8dot4
37+
// CHECK: fdot v0.2s, v0.8b, v31.8b

‎llvm/test/MC/AArch64/FP8/directive-arch.s

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,3 +19,13 @@ fmlalb v0.8h, v0.16b, v0.16b
1919
fmlalb z23.h, z13.b, z0.b[7]
2020
// CHECK: fmlalb z23.h, z13.b, z0.b[7]
2121
.arch armv9-a+nossve-fp8fma
22+
23+
.arch armv9-a+fp8dot2
24+
fdot v31.4h, v0.8b, v0.8b
25+
// CHECK: fdot v31.4h, v0.8b, v0.8b
26+
.arch armv9-a+nofp8dot2
27+
28+
.arch armv9-a+fp8dot4
29+
fdot v0.2s, v0.8b, v31.8b
30+
// CHECK: fdot v0.2s, v0.8b, v31.8b
31+
.arch armv9-a+nofp8dot4

‎llvm/test/MC/AArch64/FP8/dot-diagnostic.s

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,59 @@
1+
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+fp8dot2,+fp8dot4 2>&1 < %s| FileCheck %s
2+
3+
// --------------------------------------------------------------------------//
4+
// Element size extension incorrect
5+
6+
fdot v31.4h, v0.8h, v0.8b
7+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
8+
// CHECK-NEXT: fdot v31.4h, v0.8h, v0.8b
9+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10+
11+
fdot v31.8h, v0.16b, v31.16h
12+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
13+
// CHECK-NEXT: fdot v31.8h, v0.16b, v31.16h
14+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15+
16+
fdot v0.2s, v0.8s, v31.8b
17+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid vector kind qualifier
18+
// CHECK-NEXT: fdot v0.2s, v0.8s, v31.8b
19+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20+
21+
fdot v31.4s, v0, v31.16b
22+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
23+
// CHECK-NEXT: fdot v31.4s, v0, v31.16b
24+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25+
26+
//--------------------------------------------------------------------------//
27+
// Last Register range is between 0-15
28+
29+
fdot v31.4h, v31.8b, v16.2b[0]
30+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
31+
// CHECK-NEXT: fdot v31.4h, v31.8b, v16.2b[0]
32+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
33+
34+
fdot v0.8h, v0.16b, v16.2b[7]
35+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
36+
// CHECK-NEXT: fdot v0.8h, v0.16b, v16.2b[7]
37+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
38+
39+
// --------------------------------------------------------------------------//
40+
// Out of range index
41+
fdot v31.4h, v31.8b, v15.2b[-1]
42+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
43+
// CHECK-NEXT: fdot v31.4h, v31.8b, v15.2b[-1]
44+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
45+
46+
fdot v0.8h, v0.16b, v15.2b[8]
47+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
48+
// CHECK-NEXT: fdot v0.8h, v0.16b, v15.2b[8]
49+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
50+
51+
fdot v0.2s, v0.8b, v31.4b[-1]
52+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
53+
// CHECK-NEXT: fdot v0.2s, v0.8b, v31.4b[-1]
54+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
55+
56+
fdot v0.4s, v31.16b, v0.4b[4]
57+
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
58+
// CHECK-NEXT: fdot v0.4s, v31.16b, v0.4b[4]
59+
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

‎llvm/test/MC/AArch64/FP8/dot.s

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,63 @@
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fp8dot2,+fp8dot4 < %s \
2+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4+
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fp8dot2,+fp8dot4 < %s \
6+
// RUN: | llvm-objdump -d --mattr=+fp8dot2,+fp8dot4 - | FileCheck %s --check-prefix=CHECK-INST
7+
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fp8dot2,+fp8dot4 < %s \
8+
// RUN: | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
9+
// Disassemble encoding and check the re-encoding (-show-encoding) matches.
10+
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fp8dot2,+fp8dot4 < %s \
11+
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
12+
// RUN: | llvm-mc -triple=aarch64 -mattr=+fp8dot2,+fp8dot4 -disassemble -show-encoding \
13+
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
14+
15+
/// VECTOR
16+
fdot v31.4h, v0.8b, v0.8b
17+
// CHECK-INST: fdot v31.4h, v0.8b, v0.8b
18+
// CHECK-ENCODING: [0x1f,0xfc,0x40,0x0e]
19+
// CHECK-ERROR: instruction requires: fp8dot2
20+
// CHECK-UNKNOWN: 0e40fc1f <unknown>
21+
22+
fdot v31.8h, v0.16b, v31.16b
23+
// CHECK-INST: fdot v31.8h, v0.16b, v31.16b
24+
// CHECK-ENCODING: [0x1f,0xfc,0x5f,0x4e]
25+
// CHECK-ERROR: instruction requires: fp8dot2
26+
// CHECK-UNKNOWN: 4e5ffc1f <unknown>
27+
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fdot v0.2s, v0.8b, v31.8b
29+
// CHECK-INST: fdot v0.2s, v0.8b, v31.8b
30+
// CHECK-ENCODING: [0x00,0xfc,0x1f,0x0e]
31+
// CHECK-ERROR: instruction requires: fp8dot4
32+
// CHECK-UNKNOWN: 0e1ffc00 <unknown>
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fdot v31.4s, v0.16b, v31.16b
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// CHECK-INST: fdot v31.4s, v0.16b, v31.16b
36+
// CHECK-ENCODING: [0x1f,0xfc,0x1f,0x4e]
37+
// CHECK-ERROR: instruction requires: fp8dot4
38+
// CHECK-UNKNOWN: 4e1ffc1f <unknown>
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//INDEXED
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fdot v31.4h, v31.8b, v15.2b[0]
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// CHECK-INST: fdot v31.4h, v31.8b, v15.2b[0]
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// CHECK-ENCODING: [0xff,0x03,0x4f,0x0f]
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// CHECK-ERROR: instruction requires: fp8dot2
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// CHECK-UNKNOWN: 0f4f03ff <unknown>
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fdot v0.8h, v0.16b, v15.2b[7]
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// CHECK-INST: fdot v0.8h, v0.16b, v15.2b[7]
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// CHECK-ENCODING: [0x00,0x08,0x7f,0x4f]
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// CHECK-ERROR: instruction requires: fp8dot2
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// CHECK-UNKNOWN: 4f7f0800 <unknown>
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fdot v0.2s, v0.8b, v31.4b[0]
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// CHECK-INST: fdot v0.2s, v0.8b, v31.4b[0]
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// CHECK-ENCODING: [0x00,0x00,0x1f,0x0f]
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// CHECK-ERROR: instruction requires: fp8dot4
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// CHECK-UNKNOWN: 0f1f0000 <unknown>
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fdot v0.4s, v31.16b, v0.4b[3]
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// CHECK-INST: fdot v0.4s, v31.16b, v0.4b[3]
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// CHECK-ENCODING: [0xe0,0x0b,0x20,0x4f]
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// CHECK-ERROR: instruction requires: fp8dot4
63+
// CHECK-UNKNOWN: 4f200be0 <unknown>

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