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VyacheslavLevytskyyVyacheslavLevytskyy
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[SPIR-V] Rework usage of virtual registers' types and classes (llvm#101732)
This PR contains changes in virtual register processing aimed to improve correctness of emitted MIR between passes from the perspective of MachineVerifier. This potentially helps to detect previously missed flaws in code emission and harden the test suite. As a measure of correctness and usefulness of this PR we may use a mode with expensive checks set on, and MachineVerifier reports problems in the test suite. In order to satisfy Machine Verifier requirements to MIR correctness not only a rework of usage of virtual registers' types and classes is required, but also corrections into pre-legalizer and instruction selection logics. Namely, the following changes are introduced: * scalar virtual registers have proper bit width, * detect register class by SPIR-V type, * add a superclass for id virtual register classes, * fix Tablegen rules used for instruction selection, * fixes of minor existed issues (missed flag for proper representation of a null constant for OpenCL vs. HLSL, wrong usage of integer virtual registers as a synonym of any non-type virtual register).
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‎llvm/lib/Target/SPIRV/MCTargetDesc/SPIRVMCCodeEmitter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,7 @@ static bool hasType(const MCInst &MI, const MCInstrInfo &MII) {
6767
// Check if we define an ID, and take a type as operand 1.
6868
auto &DefOpInfo = MCDesc.operands()[0];
6969
auto &FirstArgOpInfo = MCDesc.operands()[1];
70-
return (DefOpInfo.RegClass == SPIRV::IDRegClassID ||
71-
DefOpInfo.RegClass == SPIRV::ANYIDRegClassID) &&
70+
return DefOpInfo.RegClass != SPIRV::TYPERegClassID &&
7271
FirstArgOpInfo.RegClass == SPIRV::TYPERegClassID;
7372
}
7473
return false;

‎llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp

Lines changed: 77 additions & 77 deletions
Large diffs are not rendered by default.

‎llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -372,7 +372,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
372372

373373
auto MRI = MIRBuilder.getMRI();
374374
Register FuncVReg = MRI->createGenericVirtualRegister(LLT::scalar(32));
375-
MRI->setRegClass(FuncVReg, &SPIRV::IDRegClass);
375+
MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass);
376376
if (F.isDeclaration())
377377
GR->add(&F, &MIRBuilder.getMF(), FuncVReg);
378378
FunctionType *FTy = getOriginalFunctionType(F);
@@ -403,7 +403,7 @@ bool SPIRVCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
403403
int i = 0;
404404
for (const auto &Arg : F.args()) {
405405
assert(VRegs[i].size() == 1 && "Formal arg has multiple vregs");
406-
MRI->setRegClass(VRegs[i][0], &SPIRV::IDRegClass);
406+
MRI->setRegClass(VRegs[i][0], &SPIRV::iIDRegClass);
407407
MIRBuilder.buildInstr(SPIRV::OpFunctionParameter)
408408
.addDef(VRegs[i][0])
409409
.addUse(GR->getSPIRVTypeID(ArgTypeVRegs[i]));
@@ -558,7 +558,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
558558
if (MIRBuilder.getDataLayout().getTypeStoreSize(Arg.getType()).isZero())
559559
continue; // Don't handle zero sized types.
560560
Register Reg = MRI->createGenericVirtualRegister(LLT::scalar(32));
561-
MRI->setRegClass(Reg, &SPIRV::IDRegClass);
561+
MRI->setRegClass(Reg, &SPIRV::iIDRegClass);
562562
ToInsert.push_back({Reg});
563563
VRegArgs.push_back(ToInsert.back());
564564
}
@@ -596,7 +596,7 @@ bool SPIRVCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
596596

597597
// Make sure there's a valid return reg, even for functions returning void.
598598
if (!ResVReg.isValid())
599-
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
599+
ResVReg = MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
600600
SPIRVType *RetType = GR->assignTypeToVReg(OrigRetTy, ResVReg, MIRBuilder);
601601

602602
// Emit the call instruction and its args.

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.cpp

Lines changed: 16 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -177,7 +177,7 @@ SPIRVGlobalRegistry::getOrCreateConstIntReg(uint64_t Val, SPIRVType *SpvType,
177177
// TODO: https://github.com/llvm/llvm-project/issues/88129
178178
LLT LLTy = LLT::scalar(32);
179179
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
180-
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
180+
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
181181
if (MIRBuilder)
182182
assignTypeToVReg(LLVMIntTy, Res, *MIRBuilder);
183183
else
@@ -214,7 +214,7 @@ SPIRVGlobalRegistry::getOrCreateConstFloatReg(APFloat Val, SPIRVType *SpvType,
214214
// TODO: https://github.com/llvm/llvm-project/issues/88129
215215
LLT LLTy = LLT::scalar(32);
216216
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
217-
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
217+
CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
218218
if (MIRBuilder)
219219
assignTypeToVReg(LLVMFloatTy, Res, *MIRBuilder);
220220
else
@@ -311,7 +311,7 @@ Register SPIRVGlobalRegistry::buildConstantInt(uint64_t Val,
311311
unsigned BitWidth = SpvType ? getScalarOrVectorBitWidth(SpvType) : 32;
312312
LLT LLTy = LLT::scalar(EmitIR ? BitWidth : 32);
313313
Res = MF.getRegInfo().createGenericVirtualRegister(LLTy);
314-
MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
314+
MF.getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
315315
assignTypeToVReg(LLVMIntTy, Res, MIRBuilder,
316316
SPIRV::AccessQualifier::ReadWrite, EmitIR);
317317
DT.add(ConstInt, &MIRBuilder.getMF(), Res);
@@ -354,7 +354,7 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
354354
Register Res = DT.find(ConstFP, &MF);
355355
if (!Res.isValid()) {
356356
Res = MF.getRegInfo().createGenericVirtualRegister(LLT::scalar(32));
357-
MF.getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
357+
MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass);
358358
assignSPIRVTypeToVReg(SpvType, Res, MF);
359359
DT.add(ConstFP, &MF, Res);
360360

@@ -368,11 +368,9 @@ Register SPIRVGlobalRegistry::buildConstantFP(APFloat Val,
368368
return Res;
369369
}
370370

371-
Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
372-
MachineInstr &I,
373-
SPIRVType *SpvType,
374-
const SPIRVInstrInfo &TII,
375-
unsigned BitWidth) {
371+
Register SPIRVGlobalRegistry::getOrCreateBaseRegister(
372+
Constant *Val, MachineInstr &I, SPIRVType *SpvType,
373+
const SPIRVInstrInfo &TII, unsigned BitWidth, bool ZeroAsNull) {
376374
SPIRVType *Type = SpvType;
377375
if (SpvType->getOpcode() == SPIRV::OpTypeVector ||
378376
SpvType->getOpcode() == SPIRV::OpTypeArray) {
@@ -382,12 +380,12 @@ Register SPIRVGlobalRegistry::getOrCreateBaseRegister(Constant *Val,
382380
if (Type->getOpcode() == SPIRV::OpTypeFloat) {
383381
SPIRVType *SpvBaseType = getOrCreateSPIRVFloatType(BitWidth, I, TII);
384382
return getOrCreateConstFP(dyn_cast<ConstantFP>(Val)->getValue(), I,
385-
SpvBaseType, TII);
383+
SpvBaseType, TII, ZeroAsNull);
386384
}
387385
assert(Type->getOpcode() == SPIRV::OpTypeInt);
388386
SPIRVType *SpvBaseType = getOrCreateSPIRVIntegerType(BitWidth, I, TII);
389387
return getOrCreateConstInt(Val->getUniqueInteger().getSExtValue(), I,
390-
SpvBaseType, TII);
388+
SpvBaseType, TII, ZeroAsNull);
391389
}
392390

393391
Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
@@ -404,14 +402,15 @@ Register SPIRVGlobalRegistry::getOrCreateCompositeOrNull(
404402
// TODO: can moved below once sorting of types/consts/defs is implemented.
405403
Register SpvScalConst;
406404
if (!IsNull)
407-
SpvScalConst = getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth);
405+
SpvScalConst =
406+
getOrCreateBaseRegister(Val, I, SpvType, TII, BitWidth, ZeroAsNull);
408407

409408
// TODO: handle cases where the type is not 32bit wide
410409
// TODO: https://github.com/llvm/llvm-project/issues/88129
411410
LLT LLTy = LLT::scalar(32);
412411
Register SpvVecConst =
413412
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
414-
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
413+
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
415414
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
416415
DT.add(CA, CurMF, SpvVecConst);
417416
MachineInstrBuilder MIB;
@@ -513,7 +512,7 @@ Register SPIRVGlobalRegistry::getOrCreateIntCompositeOrNull(
513512
LLT LLTy = EmitIR ? LLT::fixed_vector(ElemCnt, BitWidth) : LLT::scalar(32);
514513
Register SpvVecConst =
515514
CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
516-
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::IDRegClass);
515+
CurMF->getRegInfo().setRegClass(SpvVecConst, &SPIRV::iIDRegClass);
517516
assignSPIRVTypeToVReg(SpvType, SpvVecConst, *CurMF);
518517
DT.add(CA, CurMF, SpvVecConst);
519518
if (EmitIR) {
@@ -565,7 +564,7 @@ SPIRVGlobalRegistry::getOrCreateConstNullPtr(MachineIRBuilder &MIRBuilder,
565564
if (!Res.isValid()) {
566565
LLT LLTy = LLT::pointer(LLVMPtrTy->getAddressSpace(), PointerSize);
567566
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
568-
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
567+
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
569568
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
570569
MIRBuilder.buildInstr(SPIRV::OpConstantNull)
571570
.addDef(Res)
@@ -588,7 +587,7 @@ Register SPIRVGlobalRegistry::buildConstantSampler(
588587
auto Sampler =
589588
ResReg.isValid()
590589
? ResReg
591-
: MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::IDRegClass);
590+
: MIRBuilder.getMRI()->createVirtualRegister(&SPIRV::iIDRegClass);
592591
auto Res = MIRBuilder.buildInstr(SPIRV::OpConstantSampler)
593592
.addDef(Sampler)
594593
.addUse(getSPIRVTypeID(SampTy))
@@ -1439,7 +1438,7 @@ Register SPIRVGlobalRegistry::getOrCreateUndef(MachineInstr &I,
14391438
return Res;
14401439
LLT LLTy = LLT::scalar(32);
14411440
Res = CurMF->getRegInfo().createGenericVirtualRegister(LLTy);
1442-
CurMF->getRegInfo().setRegClass(Res, &SPIRV::IDRegClass);
1441+
CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass);
14431442
assignSPIRVTypeToVReg(SpvType, Res, *CurMF);
14441443
DT.add(UV, CurMF, Res);
14451444

‎llvm/lib/Target/SPIRV/SPIRVGlobalRegistry.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -439,8 +439,8 @@ class SPIRVGlobalRegistry {
439439
SPIRVType *finishCreatingSPIRVType(const Type *LLVMTy, SPIRVType *SpirvType);
440440
Register getOrCreateBaseRegister(Constant *Val, MachineInstr &I,
441441
SPIRVType *SpvType,
442-
const SPIRVInstrInfo &TII,
443-
unsigned BitWidth);
442+
const SPIRVInstrInfo &TII, unsigned BitWidth,
443+
bool ZeroAsNull);
444444
Register getOrCreateCompositeOrNull(Constant *Val, MachineInstr &I,
445445
SPIRVType *SpvType,
446446
const SPIRVInstrInfo &TII, Constant *CA,

‎llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -96,10 +96,10 @@ SPIRVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
9696
: &SPIRV::fIDRegClass);
9797
else if (VT.isInteger())
9898
RC = VT.isVector() ? &SPIRV::vIDRegClass
99-
: (VT.getScalarSizeInBits() > 32 ? &SPIRV::ID64RegClass
100-
: &SPIRV::IDRegClass);
99+
: (VT.getScalarSizeInBits() > 32 ? &SPIRV::iID64RegClass
100+
: &SPIRV::iIDRegClass);
101101
else
102-
RC = &SPIRV::IDRegClass;
102+
RC = &SPIRV::iIDRegClass;
103103

104104
return std::make_pair(0u, RC);
105105
}
@@ -125,7 +125,7 @@ static void doInsertBitcast(const SPIRVSubtarget &STI, MachineRegisterInfo *MRI,
125125
*STI.getRegBankInfo());
126126
if (!Res)
127127
report_fatal_error("insert validation bitcast: cannot constrain all uses");
128-
MRI->setRegClass(NewReg, &SPIRV::IDRegClass);
128+
MRI->setRegClass(NewReg, &SPIRV::iIDRegClass);
129129
GR.assignSPIRVTypeToVReg(NewPtrType, NewReg, MIB.getMF());
130130
I.getOperand(OpIdx).setReg(NewReg);
131131
}

‎llvm/lib/Target/SPIRV/SPIRVInstrInfo.td

Lines changed: 32 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -17,8 +17,8 @@ include "SPIRVSymbolicOperands.td"
1717
let isCodeGenOnly=1 in {
1818
def ASSIGN_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
1919
def DECL_TYPE: Pseudo<(outs ANYID:$dst_id), (ins ANYID:$src_id, TYPE:$src_ty)>;
20-
def GET_ID: Pseudo<(outs ID:$dst_id), (ins ANYID:$src)>;
21-
def GET_ID64: Pseudo<(outs ID64:$dst_id), (ins ANYID:$src)>;
20+
def GET_ID: Pseudo<(outs iID:$dst_id), (ins ANYID:$src)>;
21+
def GET_ID64: Pseudo<(outs iID64:$dst_id), (ins ANYID:$src)>;
2222
def GET_fID: Pseudo<(outs fID:$dst_id), (ins ANYID:$src)>;
2323
def GET_fID64: Pseudo<(outs fID64:$dst_id), (ins ANYID:$src)>;
2424
def GET_pID32: Pseudo<(outs pID32:$dst_id), (ins ANYID:$src)>;
@@ -40,18 +40,18 @@ class BinOp<string name, bits<16> opCode, list<dag> pattern=[]>
4040
"$dst = "#name#" $src_ty $src $src2", pattern>;
4141

4242
class BinOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
43-
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
44-
"$dst = "#name#" $src_ty $src $src2", [(set ID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
43+
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src, CID:$src2),
44+
"$dst = "#name#" $src_ty $src $src2", [(set iID:$dst, (assigntype (node CID:$src, CID:$src2), TYPE:$src_ty))]>;
4545

4646
class TernOpTyped<string name, bits<16> opCode, RegisterClass CCond, RegisterClass CID, SDNode node>
47-
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
48-
"$dst = "#name#" $src_ty $cond $src1 $src2", [(set ID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
47+
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CCond:$cond, CID:$src1, CID:$src2),
48+
"$dst = "#name#" $src_ty $cond $src1 $src2", [(set iID:$dst, (assigntype (node CCond:$cond, CID:$src1, CID:$src2), TYPE:$src_ty))]>;
4949

5050
multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0, bit genV = 0> {
5151
if genF then
5252
def S: BinOpTyped<name, opCode, fID, node>;
5353
else
54-
def S: BinOpTyped<name, opCode, ID, node>;
54+
def S: BinOpTyped<name, opCode, iID, node>;
5555
if genV then {
5656
if genF then
5757
def V: BinOpTyped<name, opCode, vfID, node>;
@@ -62,32 +62,32 @@ multiclass BinOpTypedGen<string name, bits<16> opCode, SDNode node, bit genF = 0
6262

6363
multiclass TernOpTypedGen<string name, bits<16> opCode, SDNode node, bit genP = 1, bit genI = 1, bit genF = 0, bit genV = 0> {
6464
if genF then {
65-
def SFSCond: TernOpTyped<name, opCode, ID, fID, node>;
65+
def SFSCond: TernOpTyped<name, opCode, iID, fID, node>;
6666
def SFVCond: TernOpTyped<name, opCode, vID, fID, node>;
6767
}
6868
if genI then {
69-
def SISCond: TernOpTyped<name, opCode, ID, ID, node>;
70-
def SIVCond: TernOpTyped<name, opCode, vID, ID, node>;
69+
def SISCond: TernOpTyped<name, opCode, iID, iID, node>;
70+
def SIVCond: TernOpTyped<name, opCode, vID, iID, node>;
7171
}
7272
if genP then {
73-
def SPSCond32: TernOpTyped<name, opCode, ID, pID32, node>;
73+
def SPSCond32: TernOpTyped<name, opCode, iID, pID32, node>;
7474
def SPVCond32: TernOpTyped<name, opCode, vID, pID32, node>;
75-
def SPSCond64: TernOpTyped<name, opCode, ID, pID64, node>;
75+
def SPSCond64: TernOpTyped<name, opCode, iID, pID64, node>;
7676
def SPVCond64: TernOpTyped<name, opCode, vID, pID64, node>;
7777
}
7878
if genV then {
7979
if genF then {
80-
def VFSCond: TernOpTyped<name, opCode, ID, vfID, node>;
80+
def VFSCond: TernOpTyped<name, opCode, iID, vfID, node>;
8181
def VFVCond: TernOpTyped<name, opCode, vID, vfID, node>;
8282
}
8383
if genI then {
84-
def VISCond: TernOpTyped<name, opCode, ID, vID, node>;
84+
def VISCond: TernOpTyped<name, opCode, iID, vID, node>;
8585
def VIVCond: TernOpTyped<name, opCode, vID, vID, node>;
8686
}
8787
if genP then {
88-
def VPSCond32: TernOpTyped<name, opCode, ID, vpID32, node>;
88+
def VPSCond32: TernOpTyped<name, opCode, iID, vpID32, node>;
8989
def VPVCond32: TernOpTyped<name, opCode, vID, vpID32, node>;
90-
def VPSCond64: TernOpTyped<name, opCode, ID, vpID64, node>;
90+
def VPSCond64: TernOpTyped<name, opCode, iID, vpID64, node>;
9191
def VPVCond64: TernOpTyped<name, opCode, vID, vpID64, node>;
9292
}
9393
}
@@ -97,8 +97,8 @@ class UnOp<string name, bits<16> opCode, list<dag> pattern=[]>
9797
: Op<opCode, (outs ANYID:$dst), (ins TYPE:$type, ANYID:$src),
9898
"$dst = "#name#" $type $src", pattern>;
9999
class UnOpTyped<string name, bits<16> opCode, RegisterClass CID, SDNode node>
100-
: Op<opCode, (outs ID:$dst), (ins TYPE:$src_ty, CID:$src),
101-
"$dst = "#name#" $src_ty $src", [(set ID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
100+
: Op<opCode, (outs iID:$dst), (ins TYPE:$src_ty, CID:$src),
101+
"$dst = "#name#" $src_ty $src", [(set iID:$dst, (assigntype (node CID:$src), TYPE:$src_ty))]>;
102102

103103
class SimpleOp<string name, bits<16> opCode>: Op<opCode, (outs), (ins), name>;
104104

@@ -240,16 +240,16 @@ def ConstPseudoFalse: IntImmLeaf<i32, [{ return Imm.getBitWidth() == 1 && Imm.ge
240240
def ConstPseudoNull: IntImmLeaf<i64, [{ return Imm.isZero(); }]>;
241241

242242
multiclass IntFPImm<bits<16> opCode, string name> {
243-
def I: Op<opCode, (outs ID:$dst), (ins TYPE:$type, ID:$src, variable_ops),
244-
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
245-
def F: Op<opCode, (outs ID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
246-
"$dst = "#name#" $type", [(set ID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
243+
def I: Op<opCode, (outs iID:$dst), (ins TYPE:$type, iID:$src, variable_ops),
244+
"$dst = "#name#" $type", [(set iID:$dst, (assigntype PseudoConstI:$src, TYPE:$type))]>;
245+
def F: Op<opCode, (outs fID:$dst), (ins TYPE:$type, fID:$src, variable_ops),
246+
"$dst = "#name#" $type", [(set fID:$dst, (assigntype PseudoConstF:$src, TYPE:$type))]>;
247247
}
248248

249-
def OpConstantTrue: Op<41, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
250-
[(set ID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
251-
def OpConstantFalse: Op<42, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
252-
[(set ID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
249+
def OpConstantTrue: Op<41, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantTrue $src_ty",
250+
[(set iID:$dst, (assigntype ConstPseudoTrue, TYPE:$src_ty))]>;
251+
def OpConstantFalse: Op<42, (outs iID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantFalse $src_ty",
252+
[(set iID:$dst, (assigntype ConstPseudoFalse, TYPE:$src_ty))]>;
253253

254254
defm OpConstant: IntFPImm<43, "OpConstant">;
255255

@@ -258,8 +258,7 @@ def OpConstantComposite: Op<44, (outs ID:$res), (ins TYPE:$type, variable_ops),
258258
def OpConstantSampler: Op<45, (outs ID:$res),
259259
(ins TYPE:$t, SamplerAddressingMode:$s, i32imm:$p, SamplerFilterMode:$f),
260260
"$res = OpConstantSampler $t $s $p $f">;
261-
def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty",
262-
[(set ID:$dst, (assigntype ConstPseudoNull, TYPE:$src_ty))]>;
261+
def OpConstantNull: Op<46, (outs ID:$dst), (ins TYPE:$src_ty), "$dst = OpConstantNull $src_ty">;
263262

264263
def OpSpecConstantTrue: Op<48, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantTrue $t">;
265264
def OpSpecConstantFalse: Op<49, (outs ID:$r), (ins TYPE:$t), "$r = OpSpecConstantFalse $t">;
@@ -469,8 +468,10 @@ def OpConvertBF16ToFINTEL : UnOp<"OpConvertBF16ToFINTEL", 6117>;
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470469
// 3.42.12 Composite Instructions
471470

471+
//def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
472+
// "$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
472473
def OpVectorExtractDynamic: Op<77, (outs ID:$res), (ins TYPE:$type, vID:$vec, ID:$idx),
473-
"$res = OpVectorExtractDynamic $type $vec $idx", [(set ID:$res, (assigntype (extractelt vID:$vec, ID:$idx), TYPE:$type))]>;
474+
"$res = OpVectorExtractDynamic $type $vec $idx">;
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475476
def OpVectorInsertDynamic: Op<78, (outs ID:$res), (ins TYPE:$ty, ID:$vec, ID:$comp, ID:$idx),
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"$res = OpVectorInsertDynamic $ty $vec $comp $idx">;
@@ -521,8 +522,8 @@ def OpMatrixTimesMatrix: BinOp<"OpMatrixTimesMatrix", 146>;
521522
def OpOuterProduct: BinOp<"OpOuterProduct", 147>;
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def OpDot: BinOp<"OpDot", 148>;
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524-
def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, ID, addc>;
525-
def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, ID, subc>;
525+
def OpIAddCarry: BinOpTyped<"OpIAddCarry", 149, iID, addc>;
526+
def OpISubBorrow: BinOpTyped<"OpISubBorrow", 150, iID, subc>;
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def OpUMulExtended: BinOp<"OpUMulExtended", 151>;
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def OpSMulExtended: BinOp<"OpSMulExtended", 152>;
528529

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