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[X86] Add test coverage for i512 shift-by-constants
Based off llvm#132601 - pass the i512 types inside 512-bit vectors Shows several missed general codegen issues that will help in a lot more cases than just this.
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‎llvm/test/CodeGen/X86/shift-i512.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw | FileCheck %s -check-prefixes=AVX512VL
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512vl,+avx512dq,+avx512bw,+avx512vbmi2 | FileCheck %s -check-prefixes=AVX512VBMI
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s -check-prefixes=ZNVER4
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; i512 shifts hidden inside 512-bit vectors.
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define <8 x i64> @shl_i512_1(<8 x i64> %a) {
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; AVX512VL-LABEL: shl_i512_1:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm2
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; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm3
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; AVX512VL-NEXT: vpaddq %xmm3, %xmm3, %xmm4
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; AVX512VL-NEXT: vpaddq %xmm2, %xmm2, %xmm5
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; AVX512VL-NEXT: vinserti128 $1, %xmm5, %ymm4, %ymm4
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; AVX512VL-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm5
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; AVX512VL-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[2,3,2,3,6,7,6,7]
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; AVX512VL-NEXT: vpsrlq $63, %ymm5, %ymm5
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; AVX512VL-NEXT: vpor %ymm5, %ymm4, %ymm4
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; AVX512VL-NEXT: vpsllq $1, %xmm0, %xmm5
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm6 = xmm0[2,3,2,3]
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; AVX512VL-NEXT: vpsrlq $63, %xmm6, %xmm7
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; AVX512VL-NEXT: vpaddq %xmm1, %xmm1, %xmm8
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; AVX512VL-NEXT: vpor %xmm7, %xmm8, %xmm7
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; AVX512VL-NEXT: vinserti128 $1, %xmm7, %ymm5, %ymm5
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; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm5 = xmm3[2,3,2,3]
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; AVX512VL-NEXT: vpaddq %xmm5, %xmm5, %xmm5
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm7 = xmm2[2,3,2,3]
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; AVX512VL-NEXT: vpaddq %xmm7, %xmm7, %xmm7
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; AVX512VL-NEXT: vinserti128 $1, %xmm7, %ymm5, %ymm5
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; AVX512VL-NEXT: vpaddq %xmm6, %xmm6, %xmm6
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[2,3,2,3]
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; AVX512VL-NEXT: vpaddq %xmm7, %xmm7, %xmm7
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; AVX512VL-NEXT: vinserti128 $1, %xmm7, %ymm6, %ymm6
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; AVX512VL-NEXT: vinserti64x4 $1, %ymm5, %zmm6, %zmm5
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; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm3, %ymm2
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; AVX512VL-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
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; AVX512VL-NEXT: vpsrlq $63, %zmm0, %zmm0
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; AVX512VL-NEXT: vporq %zmm0, %zmm5, %zmm0
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; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm4[0],zmm0[0],zmm4[2],zmm0[2],zmm4[4],zmm0[4],zmm4[6],zmm0[6]
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; AVX512VL-NEXT: retq
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;
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; AVX512VBMI-LABEL: shl_i512_1:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm2
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; AVX512VBMI-NEXT: vextracti32x4 $3, %zmm0, %xmm3
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $1, %xmm3, %xmm4, %xmm4
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $1, %xmm2, %xmm5, %xmm6
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm4, %ymm6, %ymm4
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm6 = xmm1[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $1, %xmm1, %xmm6, %xmm7
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm8 = xmm0[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $1, %xmm0, %xmm8, %xmm9
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm7, %ymm9, %ymm7
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; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm4, %zmm7, %zmm4
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; AVX512VBMI-NEXT: vpshldq $1, %xmm8, %xmm1, %xmm1
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; AVX512VBMI-NEXT: vpsllq $1, %xmm0, %xmm0
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
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; AVX512VBMI-NEXT: vpshldq $1, %xmm5, %xmm3, %xmm1
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; AVX512VBMI-NEXT: vpshldq $1, %xmm6, %xmm2, %xmm2
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
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; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm4[0],zmm0[2],zmm4[2],zmm0[4],zmm4[4],zmm0[6],zmm4[6]
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; AVX512VBMI-NEXT: retq
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;
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; ZNVER4-LABEL: shl_i512_1:
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; ZNVER4: # %bb.0:
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; ZNVER4-NEXT: vextracti32x4 $3, %zmm0, %xmm1
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; ZNVER4-NEXT: vmovq %xmm0, %rdx
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; ZNVER4-NEXT: vpextrq $1, %xmm0, %r9
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; ZNVER4-NEXT: vpextrq $1, %xmm1, %rax
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; ZNVER4-NEXT: vmovq %xmm1, %rcx
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; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm1
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; ZNVER4-NEXT: shrq $63, %rdx
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; ZNVER4-NEXT: vpextrq $1, %xmm1, %rsi
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; ZNVER4-NEXT: vmovq %xmm1, %rdi
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; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm1
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; ZNVER4-NEXT: leaq (%rdx,%r9,2), %rdx
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; ZNVER4-NEXT: shrq $63, %r9
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; ZNVER4-NEXT: vpsllq $1, %xmm0, %xmm0
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; ZNVER4-NEXT: vmovq %xmm1, %r10
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; ZNVER4-NEXT: vpextrq $1, %xmm1, %r8
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; ZNVER4-NEXT: leaq (%r9,%r10,2), %r9
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; ZNVER4-NEXT: shrq $63, %r10
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; ZNVER4-NEXT: vmovq %rdx, %xmm4
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; ZNVER4-NEXT: leaq (%r10,%r8,2), %r10
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; ZNVER4-NEXT: shrq $63, %r8
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
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; ZNVER4-NEXT: leaq (%r8,%rdi,2), %r8
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; ZNVER4-NEXT: shrq $63, %rdi
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; ZNVER4-NEXT: leaq (%rdi,%rsi,2), %rdi
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; ZNVER4-NEXT: shrq $63, %rsi
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; ZNVER4-NEXT: leaq (%rsi,%rcx,2), %rsi
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; ZNVER4-NEXT: shrq $63, %rcx
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; ZNVER4-NEXT: vmovq %r8, %xmm3
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; ZNVER4-NEXT: leaq (%rcx,%rax,2), %rax
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; ZNVER4-NEXT: vmovq %rsi, %xmm2
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; ZNVER4-NEXT: vmovq %rax, %xmm1
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
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; ZNVER4-NEXT: vmovq %rdi, %xmm2
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
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; ZNVER4-NEXT: vmovq %r10, %xmm3
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; ZNVER4-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
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; ZNVER4-NEXT: vmovq %r9, %xmm2
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; ZNVER4-NEXT: vinserti128 $1, %xmm2, %ymm0, %ymm0
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; ZNVER4-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; ZNVER4-NEXT: retq
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%d = bitcast <8 x i64> %a to i512
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%s = shl i512 %d, 1
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%r = bitcast i512 %s to <8 x i64>
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ret <8 x i64> %r
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}
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define <8 x i64> @lshr_i512_1(<8 x i64> %a) {
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; AVX512VL-LABEL: lshr_i512_1:
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; AVX512VL: # %bb.0:
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; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm2
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; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm3
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; AVX512VL-NEXT: vpsllq $63, %xmm3, %xmm4
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
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; AVX512VL-NEXT: vpsrlq $1, %xmm5, %xmm5
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; AVX512VL-NEXT: vpor %xmm5, %xmm4, %xmm4
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
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; AVX512VL-NEXT: vpsrlq $1, %xmm3, %xmm3
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; AVX512VL-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
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; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; AVX512VL-NEXT: vpsllq $63, %ymm1, %ymm1
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; AVX512VL-NEXT: vpshufd {{.*#+}} ymm2 = ymm0[2,3,2,3,6,7,6,7]
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; AVX512VL-NEXT: vpsrlq $1, %ymm2, %ymm2
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; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
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; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
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; AVX512VL-NEXT: vpsrlq $1, %zmm0, %zmm2
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; AVX512VL-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
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; AVX512VL-NEXT: vpsllq $63, %zmm0, %zmm0
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; AVX512VL-NEXT: vporq %zmm2, %zmm0, %zmm0
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; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
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; AVX512VL-NEXT: retq
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;
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; AVX512VBMI-LABEL: lshr_i512_1:
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; AVX512VBMI: # %bb.0:
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; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm1
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; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm2
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; AVX512VBMI-NEXT: vextracti32x4 $3, %zmm0, %xmm3
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $63, %xmm3, %xmm4, %xmm5
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $63, %xmm2, %xmm6, %xmm7
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm5, %ymm7, %ymm5
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $63, %xmm1, %xmm7, %xmm8
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; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm9 = xmm0[2,3,2,3]
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; AVX512VBMI-NEXT: vpshldq $63, %xmm0, %xmm9, %xmm0
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm8, %ymm0, %ymm0
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; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
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; AVX512VBMI-NEXT: vpshldq $63, %xmm7, %xmm2, %xmm2
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; AVX512VBMI-NEXT: vpshldq $63, %xmm9, %xmm1, %xmm1
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
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; AVX512VBMI-NEXT: vpshldq $63, %xmm6, %xmm3, %xmm2
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; AVX512VBMI-NEXT: vpsrlq $1, %xmm4, %xmm3
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; AVX512VBMI-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
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; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
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; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
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; AVX512VBMI-NEXT: retq
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;
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; ZNVER4-LABEL: lshr_i512_1:
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; ZNVER4: # %bb.0:
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; ZNVER4-NEXT: pushq %rbx
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; ZNVER4-NEXT: .cfi_def_cfa_offset 16
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; ZNVER4-NEXT: .cfi_offset %rbx, -16
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; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm1
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; ZNVER4-NEXT: vmovq %xmm0, %r10
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; ZNVER4-NEXT: vpextrq $1, %xmm0, %rsi
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; ZNVER4-NEXT: vpextrq $1, %xmm1, %rcx
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; ZNVER4-NEXT: vmovq %xmm1, %r9
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; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm1
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; ZNVER4-NEXT: vextracti32x4 $3, %zmm0, %xmm0
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; ZNVER4-NEXT: shrq %r10
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; ZNVER4-NEXT: vpextrq $1, %xmm0, %rax
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; ZNVER4-NEXT: vmovq %xmm0, %rdx
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; ZNVER4-NEXT: vmovq %xmm1, %rdi
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; ZNVER4-NEXT: vpextrq $1, %xmm1, %r11
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; ZNVER4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
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; ZNVER4-NEXT: movq %rdx, %r8
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; ZNVER4-NEXT: shrq %r8
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; ZNVER4-NEXT: shlq $63, %rax
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; ZNVER4-NEXT: movq %rdi, %rbx
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; ZNVER4-NEXT: shrq %rbx
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; ZNVER4-NEXT: shlq $63, %rdx
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; ZNVER4-NEXT: shlq $63, %rdi
198+
; ZNVER4-NEXT: vpsrlq $1, %xmm0, %xmm0
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; ZNVER4-NEXT: orq %r8, %rax
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; ZNVER4-NEXT: movq %r11, %r8
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; ZNVER4-NEXT: shlq $63, %r8
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; ZNVER4-NEXT: shrq %r11
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; ZNVER4-NEXT: orq %rbx, %r8
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; ZNVER4-NEXT: movq %r9, %rbx
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; ZNVER4-NEXT: orq %r11, %rdx
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; ZNVER4-NEXT: movq %rsi, %r11
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; ZNVER4-NEXT: shrq %r11
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; ZNVER4-NEXT: shlq $63, %rbx
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; ZNVER4-NEXT: shrq %r9
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; ZNVER4-NEXT: shlq $63, %rsi
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; ZNVER4-NEXT: vmovq %rax, %xmm4
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; ZNVER4-NEXT: orq %r11, %rbx
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; ZNVER4-NEXT: movq %rcx, %r11
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; ZNVER4-NEXT: shlq $63, %r11
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; ZNVER4-NEXT: shrq %rcx
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; ZNVER4-NEXT: orq %r10, %rsi
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
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; ZNVER4-NEXT: orq %r9, %r11
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; ZNVER4-NEXT: orq %rdi, %rcx
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; ZNVER4-NEXT: vmovq %rbx, %xmm3
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; ZNVER4-NEXT: vmovq %rcx, %xmm1
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; ZNVER4-NEXT: vmovq %r11, %xmm2
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; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
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; ZNVER4-NEXT: vmovq %rsi, %xmm2
225+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
226+
; ZNVER4-NEXT: vmovq %r8, %xmm3
227+
; ZNVER4-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
228+
; ZNVER4-NEXT: vmovq %rdx, %xmm2
229+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
230+
; ZNVER4-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0
231+
; ZNVER4-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
232+
; ZNVER4-NEXT: popq %rbx
233+
; ZNVER4-NEXT: .cfi_def_cfa_offset 8
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; ZNVER4-NEXT: retq
235+
%d = bitcast <8 x i64> %a to i512
236+
%s = lshr i512 %d, 1
237+
%r = bitcast i512 %s to <8 x i64>
238+
ret <8 x i64> %r
239+
}
240+
241+
define <8 x i64> @ashr_i512_1(<8 x i64> %a) {
242+
; AVX512VL-LABEL: ashr_i512_1:
243+
; AVX512VL: # %bb.0:
244+
; AVX512VL-NEXT: vextracti128 $1, %ymm0, %xmm1
245+
; AVX512VL-NEXT: vextracti32x4 $2, %zmm0, %xmm2
246+
; AVX512VL-NEXT: vextracti32x4 $3, %zmm0, %xmm3
247+
; AVX512VL-NEXT: vpsllq $63, %xmm3, %xmm4
248+
; AVX512VL-NEXT: vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
249+
; AVX512VL-NEXT: vpsrlq $1, %xmm5, %xmm5
250+
; AVX512VL-NEXT: vpor %xmm5, %xmm4, %xmm4
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; AVX512VL-NEXT: vpshufd {{.*#+}} xmm3 = xmm3[2,3,2,3]
252+
; AVX512VL-NEXT: vpsraq $1, %xmm3, %xmm3
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; AVX512VL-NEXT: vinserti128 $1, %xmm3, %ymm4, %ymm3
254+
; AVX512VL-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
255+
; AVX512VL-NEXT: vpsllq $63, %ymm1, %ymm1
256+
; AVX512VL-NEXT: vpshufd {{.*#+}} ymm2 = ymm0[2,3,2,3,6,7,6,7]
257+
; AVX512VL-NEXT: vpsrlq $1, %ymm2, %ymm2
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; AVX512VL-NEXT: vpor %ymm2, %ymm1, %ymm1
259+
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm1, %zmm1
260+
; AVX512VL-NEXT: vpsrlq $1, %zmm0, %zmm2
261+
; AVX512VL-NEXT: vpshufd {{.*#+}} zmm0 = zmm0[2,3,2,3,6,7,6,7,10,11,10,11,14,15,14,15]
262+
; AVX512VL-NEXT: vpsllq $63, %zmm0, %zmm0
263+
; AVX512VL-NEXT: vporq %zmm2, %zmm0, %zmm0
264+
; AVX512VL-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
265+
; AVX512VL-NEXT: retq
266+
;
267+
; AVX512VBMI-LABEL: ashr_i512_1:
268+
; AVX512VBMI: # %bb.0:
269+
; AVX512VBMI-NEXT: vextracti128 $1, %ymm0, %xmm1
270+
; AVX512VBMI-NEXT: vextracti32x4 $2, %zmm0, %xmm2
271+
; AVX512VBMI-NEXT: vextracti32x4 $3, %zmm0, %xmm3
272+
; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm4 = xmm3[2,3,2,3]
273+
; AVX512VBMI-NEXT: vpshldq $63, %xmm3, %xmm4, %xmm5
274+
; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm6 = xmm2[2,3,2,3]
275+
; AVX512VBMI-NEXT: vpshldq $63, %xmm2, %xmm6, %xmm7
276+
; AVX512VBMI-NEXT: vinserti128 $1, %xmm5, %ymm7, %ymm5
277+
; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm7 = xmm1[2,3,2,3]
278+
; AVX512VBMI-NEXT: vpshldq $63, %xmm1, %xmm7, %xmm8
279+
; AVX512VBMI-NEXT: vpshufd {{.*#+}} xmm9 = xmm0[2,3,2,3]
280+
; AVX512VBMI-NEXT: vpshldq $63, %xmm0, %xmm9, %xmm0
281+
; AVX512VBMI-NEXT: vinserti128 $1, %xmm8, %ymm0, %ymm0
282+
; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm5, %zmm0, %zmm0
283+
; AVX512VBMI-NEXT: vpshldq $63, %xmm7, %xmm2, %xmm2
284+
; AVX512VBMI-NEXT: vpshldq $63, %xmm9, %xmm1, %xmm1
285+
; AVX512VBMI-NEXT: vinserti128 $1, %xmm2, %ymm1, %ymm1
286+
; AVX512VBMI-NEXT: vpshldq $63, %xmm6, %xmm3, %xmm2
287+
; AVX512VBMI-NEXT: vpsraq $1, %xmm4, %xmm3
288+
; AVX512VBMI-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
289+
; AVX512VBMI-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1
290+
; AVX512VBMI-NEXT: vpunpcklqdq {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[2],zmm1[2],zmm0[4],zmm1[4],zmm0[6],zmm1[6]
291+
; AVX512VBMI-NEXT: retq
292+
;
293+
; ZNVER4-LABEL: ashr_i512_1:
294+
; ZNVER4: # %bb.0:
295+
; ZNVER4-NEXT: pushq %rbx
296+
; ZNVER4-NEXT: .cfi_def_cfa_offset 16
297+
; ZNVER4-NEXT: .cfi_offset %rbx, -16
298+
; ZNVER4-NEXT: vextracti128 $1, %ymm0, %xmm1
299+
; ZNVER4-NEXT: vmovq %xmm0, %r10
300+
; ZNVER4-NEXT: vpextrq $1, %xmm0, %rsi
301+
; ZNVER4-NEXT: vpextrq $1, %xmm1, %rcx
302+
; ZNVER4-NEXT: vmovq %xmm1, %r9
303+
; ZNVER4-NEXT: vextracti32x4 $2, %zmm0, %xmm1
304+
; ZNVER4-NEXT: vextracti32x4 $3, %zmm0, %xmm0
305+
; ZNVER4-NEXT: shrq %r10
306+
; ZNVER4-NEXT: vpextrq $1, %xmm0, %rax
307+
; ZNVER4-NEXT: vmovq %xmm0, %rdx
308+
; ZNVER4-NEXT: vmovq %xmm1, %rdi
309+
; ZNVER4-NEXT: vpextrq $1, %xmm1, %r11
310+
; ZNVER4-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
311+
; ZNVER4-NEXT: movq %rdx, %r8
312+
; ZNVER4-NEXT: shrq %r8
313+
; ZNVER4-NEXT: shlq $63, %rax
314+
; ZNVER4-NEXT: movq %rdi, %rbx
315+
; ZNVER4-NEXT: shrq %rbx
316+
; ZNVER4-NEXT: shlq $63, %rdx
317+
; ZNVER4-NEXT: shlq $63, %rdi
318+
; ZNVER4-NEXT: vpsraq $1, %xmm0, %xmm0
319+
; ZNVER4-NEXT: orq %r8, %rax
320+
; ZNVER4-NEXT: movq %r11, %r8
321+
; ZNVER4-NEXT: shlq $63, %r8
322+
; ZNVER4-NEXT: shrq %r11
323+
; ZNVER4-NEXT: orq %rbx, %r8
324+
; ZNVER4-NEXT: movq %r9, %rbx
325+
; ZNVER4-NEXT: orq %r11, %rdx
326+
; ZNVER4-NEXT: movq %rsi, %r11
327+
; ZNVER4-NEXT: shrq %r11
328+
; ZNVER4-NEXT: shlq $63, %rbx
329+
; ZNVER4-NEXT: shrq %r9
330+
; ZNVER4-NEXT: shlq $63, %rsi
331+
; ZNVER4-NEXT: vmovq %rax, %xmm4
332+
; ZNVER4-NEXT: orq %r11, %rbx
333+
; ZNVER4-NEXT: movq %rcx, %r11
334+
; ZNVER4-NEXT: shlq $63, %r11
335+
; ZNVER4-NEXT: shrq %rcx
336+
; ZNVER4-NEXT: orq %r10, %rsi
337+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm4[0],xmm0[0]
338+
; ZNVER4-NEXT: orq %r9, %r11
339+
; ZNVER4-NEXT: orq %rdi, %rcx
340+
; ZNVER4-NEXT: vmovq %rbx, %xmm3
341+
; ZNVER4-NEXT: vmovq %rcx, %xmm1
342+
; ZNVER4-NEXT: vmovq %r11, %xmm2
343+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm2[0],xmm1[0]
344+
; ZNVER4-NEXT: vmovq %rsi, %xmm2
345+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
346+
; ZNVER4-NEXT: vmovq %r8, %xmm3
347+
; ZNVER4-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1
348+
; ZNVER4-NEXT: vmovq %rdx, %xmm2
349+
; ZNVER4-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm3[0],xmm2[0]
350+
; ZNVER4-NEXT: vinserti128 $1, %xmm0, %ymm2, %ymm0
351+
; ZNVER4-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0
352+
; ZNVER4-NEXT: popq %rbx
353+
; ZNVER4-NEXT: .cfi_def_cfa_offset 8
354+
; ZNVER4-NEXT: retq
355+
%d = bitcast <8 x i64> %a to i512
356+
%s = ashr i512 %d, 1
357+
%r = bitcast i512 %s to <8 x i64>
358+
ret <8 x i64> %r
359+
}

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