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[NFC][InstCombine][AArch64] Add simplify tests for reversed SVE intrinsics.
Add missing tests for fdivr, fsubr, sdivr, subr & udivr. Add test case to demonstrate incorrect poison propagation.
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‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll

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@@ -103,6 +103,16 @@ define <vscale x 4 x i32> @constant_mul_u_after_striping_inactive_lanes(<vscale
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ret <vscale x 4 x i32> %3
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}
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; SVE intrinsics don't have the same poison propagation rules as the IR.
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define <vscale x 4 x i32> @dont_propagate_poison(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @dont_propagate_poison(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]], <vscale x 4 x i32> [[A:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: ret <vscale x 4 x i32> poison
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> poison, <vscale x 4 x i32> splat (i32 1))
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ret <vscale x 4 x i32> %r
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}
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; The follow tests demonstrate the operations for which hooks are in place to
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; enable simplification. Given the simplications themselves are common code, it
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; is assumed they are already well tested elsewhere.
@@ -202,6 +212,16 @@ define <vscale x 4 x float> @constant_fdiv_u(<vscale x 4 x i1> %pg) #0 {
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @constant_fdivr(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x float> @constant_fdivr(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 6.000000e+00), <vscale x 4 x float> splat (float 1.200000e+01))
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; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
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;
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 6.0), <vscale x 4 x float> splat (float 12.0))
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @constant_fmul(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x float> @constant_fmul(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -240,6 +260,16 @@ define <vscale x 4 x float> @constant_fsub_u(<vscale x 4 x i1> %pg) #0 {
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x float> @constant_fsubr(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x float> @constant_fsubr(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 6.000000e+00), <vscale x 4 x float> splat (float 7.000000e+00))
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; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
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;
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%r = call <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 6.0), <vscale x 4 x float> splat (float 7.0))
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ret <vscale x 4 x float> %r
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}
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define <vscale x 4 x i32> @constant_mul(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_mul(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -341,6 +371,39 @@ define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(<vscale x 4 x i1> %pg)
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -2147483648), <vscale x 4 x i32> splat (i32 -1))
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ret <vscale x 4 x i32> %r
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}
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define <vscale x 4 x i32> @constant_sdivr(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 -7))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
380+
;
381+
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 -7))
382+
ret <vscale x 4 x i32> %r
383+
}
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; The intrinsic's IR equivalent does not support divide-by-zero.
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define <vscale x 4 x i32> @constant_sdivr_by_zero(<vscale x 4 x i1> %pg) #0 {
387+
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr_by_zero(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 -7))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
392+
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 0), <vscale x 4 x i32> splat (i32 -7))
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ret <vscale x 4 x i32> %r
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}
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; The intrinsic's IR equivalent does not support overflow.
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define <vscale x 4 x i32> @constant_sdivr_with_overflow(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_sdivr_with_overflow(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 -1), <vscale x 4 x i32> splat (i32 -2147483648))
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ret <vscale x 4 x i32> %r
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}
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define <vscale x 4 x i32> @constant_sub(<vscale x 4 x i1> %pg) #0 {
345408
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -360,6 +423,16 @@ define <vscale x 4 x i32> @constant_sub_u(<vscale x 4 x i1> %pg) #0 {
360423
ret <vscale x 4 x i32> %r
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}
362425

426+
define <vscale x 4 x i32> @constant_subr(<vscale x 4 x i1> %pg) #0 {
427+
; CHECK-LABEL: define <vscale x 4 x i32> @constant_subr(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
432+
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
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ret <vscale x 4 x i32> %r
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}
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define <vscale x 4 x i32> @constant_udiv(<vscale x 4 x i1> %pg) #0 {
364437
; CHECK-LABEL: define <vscale x 4 x i32> @constant_udiv(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
@@ -402,6 +475,27 @@ define <vscale x 4 x i32> @constant_udiv_u_by_zero(<vscale x 4 x i1> %pg) #0 {
402475
ret <vscale x 4 x i32> %r
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}
404477

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define <vscale x 4 x i32> @constant_udivr(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_udivr(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 7))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
484+
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 3), <vscale x 4 x i32> splat (i32 7))
485+
ret <vscale x 4 x i32> %r
486+
}
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; The intrinsic's IR equivalent does not support divide-by-zero.
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define <vscale x 4 x i32> @constant_udivr_by_zero(<vscale x 4 x i1> %pg) #0 {
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; CHECK-LABEL: define <vscale x 4 x i32> @constant_udivr_by_zero(
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; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
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; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> zeroinitializer, <vscale x 4 x i32> splat (i32 7))
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; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
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;
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%r = call <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 0), <vscale x 4 x i32> splat (i32 7))
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ret <vscale x 4 x i32> %r
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}
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declare <vscale x 4 x i32> @llvm.aarch64.sve.dup.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, i32)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
@@ -410,8 +504,11 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1>, <vsc
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declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
509+
declare <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.udivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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416513
declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
@@ -424,8 +521,10 @@ declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1>, <
424521

425522
declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
426523
declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
524+
declare <vscale x 4 x float> @llvm.aarch64.sve.fdivr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
427525
declare <vscale x 4 x float> @llvm.aarch64.sve.fmul.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
428526
declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
527+
declare <vscale x 4 x float> @llvm.aarch64.sve.fsubr.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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430529
declare <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
431530
declare <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)

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