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Kenovchuravy
Keno
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Correct register class for pseudo instructions
This constrains the Mov* and similar pseudo instruction to take GPR64common register classes rather than GPR64. GPR64 includs XZR which is invalid here, because this pseudo instructions expands into an adrp/add pair sharing a destination register. XZR is invalid on add and attempting to encode it will instead increment the stack pointer causing crashes (downstream report at [1]). The test case there reproduces on LLVM11, but I do not have a test case that reaches this code path on main, since it is being masked by improved dead code elimination introduced in D91513. Nevertheless, this seems like a good thing to fix in case there are other cases that dead code elimination doesn't clean up (e.g. if `optnone` is used and the optimization is skipped). I think it would be worth auditing uses of GPR64 in pseudo instructions to see if there are any similar issues, but I do not have a high enough view of the backend or knowledge of the Aarch64 architecture to do this quickly. [1] JuliaLang/julia#39818 Reviewed By: t.p.northover Differential Revision: https://reviews.llvm.org/D97435 (cherry picked from commit 089b115)
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‎llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1049,6 +1049,7 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
10491049
case AArch64::MOVaddrEXT: {
10501050
// Expand into ADRP + ADD.
10511051
Register DstReg = MI.getOperand(0).getReg();
1052+
assert(DstReg != AArch64::XZR);
10521053
MachineInstrBuilder MIB1 =
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BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
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.add(MI.getOperand(1));

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -673,49 +673,49 @@ let isReMaterializable = 1, isCodeGenOnly = 1 in {
673673
// removed, along with the AArch64Wrapper node.
674674

675675
let AddedComplexity = 10 in
676-
def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
677-
[(set GPR64:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
676+
def LOADgot : Pseudo<(outs GPR64common:$dst), (ins i64imm:$addr),
677+
[(set GPR64common:$dst, (AArch64LOADgot tglobaladdr:$addr))]>,
678678
Sched<[WriteLDAdr]>;
679679

680680
// The MOVaddr instruction should match only when the add is not folded
681681
// into a load or store address.
682682
def MOVaddr
683-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
684-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
683+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
684+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaladdr:$hi),
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tglobaladdr:$low))]>,
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Sched<[WriteAdrAdr]>;
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def MOVaddrJT
688-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
689-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
688+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
689+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp tjumptable:$hi),
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tjumptable:$low))]>,
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Sched<[WriteAdrAdr]>;
692692
def MOVaddrCP
693-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
694-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
693+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
694+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp tconstpool:$hi),
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tconstpool:$low))]>,
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Sched<[WriteAdrAdr]>;
697697
def MOVaddrBA
698-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
699-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
698+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
699+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp tblockaddress:$hi),
700700
tblockaddress:$low))]>,
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Sched<[WriteAdrAdr]>;
702702
def MOVaddrTLS
703-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
704-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
703+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
704+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp tglobaltlsaddr:$hi),
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tglobaltlsaddr:$low))]>,
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Sched<[WriteAdrAdr]>;
707707
def MOVaddrEXT
708-
: Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
709-
[(set GPR64:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
708+
: Pseudo<(outs GPR64common:$dst), (ins i64imm:$hi, i64imm:$low),
709+
[(set GPR64common:$dst, (AArch64addlow (AArch64adrp texternalsym:$hi),
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texternalsym:$low))]>,
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Sched<[WriteAdrAdr]>;
712712
// Normally AArch64addlow either gets folded into a following ldr/str,
713713
// or together with an adrp into MOVaddr above. For cases with TLS, it
714714
// might appear without either of them, so allow lowering it into a plain
715715
// add.
716716
def ADDlowTLS
717-
: Pseudo<(outs GPR64:$dst), (ins GPR64:$src, i64imm:$low),
718-
[(set GPR64:$dst, (AArch64addlow GPR64:$src,
717+
: Pseudo<(outs GPR64sp:$dst), (ins GPR64sp:$src, i64imm:$low),
718+
[(set GPR64sp:$dst, (AArch64addlow GPR64sp:$src,
719719
tglobaltlsaddr:$low))]>,
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Sched<[WriteAdr]>;
721721

‎llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,9 +30,10 @@ registers:
3030
body: |
3131
; CHECK-LABEL: name: test_blockaddress
3232
; CHECK: bb.0 (%ir-block.0):
33-
; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64 = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
33+
; CHECK: [[MOVaddrBA:%[0-9]+]]:gpr64common = MOVaddrBA target-flags(aarch64-page) blockaddress(@test_blockaddress, %ir-block.block), target-flags(aarch64-pageoff, aarch64-nc) blockaddress(@test_blockaddress, %ir-block.block)
3434
; CHECK: [[MOVaddr:%[0-9]+]]:gpr64common = MOVaddr target-flags(aarch64-page) @addr, target-flags(aarch64-pageoff, aarch64-nc) @addr
35-
; CHECK: STRXui [[MOVaddrBA]], [[MOVaddr]], 0 :: (store (p0) into @addr)
35+
; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY [[MOVaddrBA]]
36+
; CHECK: STRXui [[COPY]], [[MOVaddr]], 0 :: (store (p0) into @addr)
3637
; CHECK: BR [[MOVaddrBA]]
3738
; CHECK: bb.1.block (address-taken):
3839
; CHECK: RET_ReallyLR

‎llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt-constrain.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ body: |
3030
; CHECK: Bcc 8, %bb.3, implicit $nzcv
3131
; CHECK: bb.1:
3232
; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
33-
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
33+
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
3434
; CHECK: early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
3535
; CHECK: BR %6
3636
; CHECK: bb.2:

‎llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ body: |
6565
; CHECK: bb.1.entry:
6666
; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
6767
; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
68-
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
68+
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
6969
; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
7070
; CHECK: BR %18
7171
; CHECK: bb.2.sw.bb:

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