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NikitaRudenkoIntelsvenvh
authored and
AlexeySachkov
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Fix visitUIToFPInst method in SPIRVLowerBool
The method did not handle correctly the case where operand of UIToFPInst instruction is vector. This patch fixes it. Co-authored-by: Sven van Haastregt <[email protected]>
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2 files changed

+171
-23
lines changed

2 files changed

+171
-23
lines changed

‎lib/SPIRV/SPIRVLowerBool.cpp

Lines changed: 19 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -77,26 +77,35 @@ class SPIRVLowerBool : public ModulePass, public InstVisitor<SPIRVLowerBool> {
7777
replace(&I, Cmp);
7878
}
7979
}
80-
void handleCastInstructions(Instruction &I) {
80+
void handleExtInstructions(Instruction &I) {
8181
auto Op = I.getOperand(0);
8282
if (isBoolType(Op->getType())) {
8383
auto Opcode = I.getOpcode();
84-
auto Ty = (Opcode == Instruction::ZExt || Opcode == Instruction::SExt)
85-
? I.getType()
86-
: Type::getInt32Ty(*Context);
84+
auto Ty = I.getType();
8785
auto Zero = getScalarOrVectorConstantInt(Ty, 0, false);
8886
auto One = getScalarOrVectorConstantInt(
8987
Ty, (Opcode == Instruction::SExt) ? ~0 : 1, false);
9088
assert(Zero && One && "Couldn't create constant int");
9189
auto Sel = SelectInst::Create(Op, One, Zero, "", &I);
92-
if (Opcode == Instruction::ZExt || Opcode == Instruction::SExt)
93-
replace(&I, Sel);
94-
else if (Opcode == Instruction::UIToFP || Opcode == Instruction::SIToFP)
95-
I.setOperand(0, Sel);
90+
replace(&I, Sel);
91+
}
92+
}
93+
void handleCastInstructions(Instruction &I) {
94+
auto Op = I.getOperand(0);
95+
auto *OpTy = Op->getType();
96+
if (isBoolType(OpTy)) {
97+
Type *Ty = Type::getInt32Ty(*Context);
98+
if (auto VT = dyn_cast<FixedVectorType>(OpTy))
99+
Ty = llvm::FixedVectorType::get(Ty, VT->getNumElements());
100+
auto Zero = getScalarOrVectorConstantInt(Ty, 0, false);
101+
auto One = getScalarOrVectorConstantInt(Ty, 1, false);
102+
assert(Zero && One && "Couldn't create constant int");
103+
auto Sel = SelectInst::Create(Op, One, Zero, "", &I);
104+
I.setOperand(0, Sel);
96105
}
97106
}
98-
virtual void visitZExtInst(ZExtInst &I) { handleCastInstructions(I); }
99-
virtual void visitSExtInst(SExtInst &I) { handleCastInstructions(I); }
107+
virtual void visitZExtInst(ZExtInst &I) { handleExtInstructions(I); }
108+
virtual void visitSExtInst(SExtInst &I) { handleExtInstructions(I); }
100109
virtual void visitUIToFPInst(UIToFPInst &I) { handleCastInstructions(I); }
101110
virtual void visitSIToFPInst(SIToFPInst &I) { handleCastInstructions(I); }
102111
bool runOnModule(Module &M) override {

‎test/uitofp-with-bool.ll

100644100755
Lines changed: 152 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,10 @@
11
; RUN: llvm-as %s -o %t.bc
2-
; RUN: llvm-spirv %t.bc -spirv-text -o - | FileCheck %s
32
; RUN: llvm-spirv %t.bc -o %t.spv
3+
; RUN: llvm-spirv %t.spv -o %t.spt --to-text
4+
; RUN: llvm-spirv -r -spirv-target-env="SPV-IR" %t.spv -o %t.bc
5+
; RUN: llvm-dis %t.bc -o %t.ll
6+
; RUN: FileCheck %s --input-file %t.spt -check-prefix=SPV
7+
; RUN: FileCheck %s --input-file %t.ll -check-prefix=LLVM
48
; RUN: spirv-val %t.spv
59

610
; The IR was generated from the following source:
@@ -11,29 +15,164 @@
1115
; Command line:
1216
; clang -x cl -cl-std=CL2.0 -target spir64 -emit-llvm -S -c test.cl
1317

14-
; CHECK: TypeInt [[int_32:[0-9]+]] 32 0
15-
; CHECK: Constant {{[0-9]+}} [[zero:[0-9]+]] 0
16-
; CHECK: Constant {{[0-9]+}} [[one:[0-9]+]] 1
17-
; CHECK: TypeBool [[bool:[0-9]+]]
1818

19-
; CHECK: Function
20-
; CHECK: FunctionParameter {{[0-9]+}} [[A:[0-9]+]]
21-
; CHECK: FunctionParameter {{[0-9]+}} [[B:[0-9]+]]
22-
; CHECK: SGreaterThan [[bool]] [[cmp_res:[0-9]+]] [[B]] [[zero]]
23-
; CHECK: Select [[int_32]] [[select_res:[0-9]+]] [[cmp_res]] [[one]] [[zero]]
24-
; CHECK: ConvertUToF {{[0-9]+}} [[utof_res:[0-9]+]] [[select_res]]
25-
; CHECK: Store [[A]] [[utof_res]]
19+
; SPV-DAG: Name [[s1:[0-9]+]] "s1"
20+
; SPV-DAG: Name [[s2:[0-9]+]] "s2"
21+
; SPV-DAG: Name [[s3:[0-9]+]] "s3"
22+
; SPV-DAG: Name [[s4:[0-9]+]] "s4"
23+
; SPV-DAG: Name [[s5:[0-9]+]] "s5"
24+
; SPV-DAG: Name [[s6:[0-9]+]] "s6"
25+
; SPV-DAG: Name [[s7:[0-9]+]] "s7"
26+
; SPV-DAG: Name [[s8:[0-9]+]] "s8"
27+
; SPV-DAG: Name [[z1:[0-9]+]] "z1"
28+
; SPV-DAG: Name [[z2:[0-9]+]] "z2"
29+
; SPV-DAG: Name [[z3:[0-9]+]] "z3"
30+
; SPV-DAG: Name [[z4:[0-9]+]] "z4"
31+
; SPV-DAG: Name [[z5:[0-9]+]] "z5"
32+
; SPV-DAG: Name [[z6:[0-9]+]] "z6"
33+
; SPV-DAG: Name [[z7:[0-9]+]] "z7"
34+
; SPV-DAG: Name [[z8:[0-9]+]] "z8"
35+
; SPV-DAG: Name [[ufp1:[0-9]+]] "ufp1"
36+
; SPV-DAG: Name [[ufp2:[0-9]+]] "ufp2"
37+
; SPV-DAG: Name [[sfp1:[0-9]+]] "sfp1"
38+
; SPV-DAG: Name [[sfp2:[0-9]+]] "sfp2"
39+
; SPV-DAG: TypeInt [[int_32:[0-9]+]] 32 0
40+
; SPV-DAG: TypeInt [[int_8:[0-9]+]] 8 0
41+
; SPV-DAG: TypeInt [[int_16:[0-9]+]] 16 0
42+
; SPV-DAG: TypeInt [[int_64:[0-9]+]] 64 0
43+
; SPV-DAG: Constant [[int_32]] [[zero_32:[0-9]+]] 0
44+
; SPV-DAG: Constant [[int_32]] [[one_32:[0-9]+]] 1
45+
; SPV-DAG: Constant [[int_8]] [[zero_8:[0-9]+]] 0
46+
; SPV-DAG: Constant [[int_8]] [[mone_8:[0-9]+]] 255
47+
; SPV-DAG: Constant [[int_16]] [[zero_16:[0-9]+]] 0
48+
; SPV-DAG: Constant [[int_16]] [[mone_16:[0-9]+]] 65535
49+
; SPV-DAG: Constant [[int_32]] [[mone_32:[0-9]+]] 4294967295
50+
; SPV-DAG: Constant [[int_64]] [[zero_64:[0-9]+]] 0 0
51+
; SPV-DAG: Constant [[int_64]] [[mone_64:[0-9]+]] 4294967295 4294967295
52+
; SPV-DAG: Constant [[int_8]] [[one_8:[0-9]+]] 1
53+
; SPV-DAG: Constant [[int_16]] [[one_16:[0-9]+]] 1
54+
; SPV-DAG: Constant [[int_64]] [[one_64:[0-9]+]] 1 0
55+
; SPV-DAG: TypeVoid [[void:[0-9]+]]
56+
; SPV-DAG: TypeFloat [[float:[0-9]+]] 32
57+
; SPV-DAG: TypeBool [[bool:[0-9]+]]
58+
; SPV-DAG: TypeVector [[vec_8:[0-9]+]] [[int_8]] 2
59+
; SPV-DAG: TypeVector [[vec_1:[0-9]+]] [[bool]] 2
60+
; SPV-DAG: TypeVector [[vec_16:[0-9]+]] [[int_16]] 2
61+
; SPV-DAG: TypeVector [[vec_32:[0-9]+]] [[int_32]] 2
62+
; SPV-DAG: TypeVector [[vec_64:[0-9]+]] [[int_64]] 2
63+
; SPV-DAG: TypeVector [[vec_float:[0-9]+]] [[float]] 2
64+
; SPV-DAG: ConstantTrue [[bool]] [[true:[0-9]+]]
65+
; SPV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
66+
; SPV-DAG: ConstantNull [[vec_8]] [[zeros_8:[0-9]+]]
67+
; SPV-DAG: ConstantComposite [[vec_8]] [[mones_8:[0-9]+]] [[mone_8]] [[mone_8]]
68+
; SPV-DAG: ConstantComposite [[vec_1]] [[true_false:[0-9]+]] [[true]] [[false]]
69+
; SPV-DAG: ConstantNull [[vec_16]] [[zeros_16:[0-9]+]]
70+
; SPV-DAG: ConstantComposite [[vec_16]] [[mones_16:[0-9]+]] [[mone_16]] [[mone_16]]
71+
; SPV-DAG: ConstantNull [[vec_1]] [[zeros_1:[0-9]+]]
72+
; SPV-DAG: ConstantNull [[vec_32]] [[zeros_32:[0-9]+]]
73+
; SPV-DAG: ConstantComposite [[vec_32]] [[mones_32:[0-9]+]] [[mone_32]] [[mone_32]]
74+
; SPV-DAG: ConstantComposite [[vec_1]] [[false_true:[0-9]+]] [[false]] [[true]]
75+
; SPV-DAG: ConstantNull [[vec_64]] [[zeros_64:[0-9]+]]
76+
; SPV-DAG: ConstantComposite [[vec_64]] [[mones_64:[0-9]+]] [[mone_64]] [[mone_64]]
77+
; SPV-DAG: ConstantComposite [[vec_1]] [[ones_1:[0-9]+]] [[true]] [[true]]
78+
; SPV-DAG: ConstantComposite [[vec_8]] [[ones_8:[0-9]+]] [[one_8]] [[one_8]]
79+
; SPV-DAG: ConstantComposite [[vec_16]] [[ones_16:[0-9]+]] [[one_16]] [[one_16]]
80+
; SPV-DAG: ConstantComposite [[vec_32]] [[ones_32:[0-9]+]] [[one_32]] [[one_32]]
81+
; SPV-DAG: ConstantComposite [[vec_64]] [[ones_64:[0-9]+]] [[one_64]] [[one_64]]
2682

2783

2884
target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-n8:16:32:64"
2985
target triple = "spir64"
3086

87+
; SPV-DAG: Function
88+
; SPV-DAG: FunctionParameter {{[0-9]+}} [[A:[0-9]+]]
89+
; SPV-DAG: FunctionParameter {{[0-9]+}} [[B:[0-9]+]]
90+
3191
; Function Attrs: nofree norecurse nounwind writeonly
3292
define dso_local spir_kernel void @K(float addrspace(1)* nocapture %A, i32 %B) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
3393
entry:
94+
95+
96+
; SPV-DAG: SGreaterThan [[bool]] [[cmp_res:[0-9]+]] [[B]] [[zero_32]]
97+
; LLVM-DAG: %cmp = icmp sgt i32 %B, 0
3498
%cmp = icmp sgt i32 %B, 0
99+
; SPV-DAG: Select [[int_32]] [[select_res:[0-9]+]] [[cmp_res]] [[one_32]] [[zero_32]]
100+
; SPV-DAG: ConvertUToF [[float]] [[utof_res:[0-9]+]] [[select_res]]
101+
; LLVM-DAG: %[[sel_res_0:[0-9]+]] = select i1 %cmp, i32 1, i32 0
102+
; LLVM-DAG: %conv = uitofp i32 %[[sel_res_0]] to float
35103
%conv = uitofp i1 %cmp to float
36-
store float %conv, float addrspace(1)* %A, align 4
104+
; SPV-DAG: Store [[A]] [[utof_res]]
105+
; LLVM-DAG: store float %conv, float addrspace(1)* %A, align 4
106+
store float %conv, float addrspace(1)* %A, align 4;
107+
108+
; SPV-DAG: Select [[int_8]] [[s1]] [[true]] [[mone_8]] [[zero_8]]
109+
; LLVM-DAG: %s1 = select i1 true, i8 -1, i8 0
110+
%s1 = sext i1 1 to i8
111+
; SPV-DAG: Select [[int_16]] [[s2]] [[false]] [[mone_16]] [[zero_16]]
112+
; LLVM-DAG: %s2 = select i1 false, i16 -1, i16 0
113+
%s2 = sext i1 0 to i16
114+
; SPV-DAG: Select [[int_32]] [[s3]] [[true]] [[mone_32]] [[zero_32]]
115+
; LLVM-DAG: %s3 = select i1 true, i32 -1, i32 0
116+
%s3 = sext i1 1 to i32
117+
; SPV-DAG: Select [[int_64]] [[s4]] [[true]] [[mone_64]] [[zero_64]]
118+
; LLVM-DAG: %s4 = select i1 true, i64 -1, i64 0
119+
%s4 = sext i1 1 to i64
120+
; SPV-DAG: Select [[vec_8]] [[s5]] [[true_false]] [[mones_8]] [[zeros_8]]
121+
; LLVM-DAG: %s5 = select <2 x i1> <i1 true, i1 false>, <2 x i8> <i8 -1, i8 -1>, <2 x i8> zeroinitializer
122+
%s5 = sext <2 x i1> <i1 1, i1 0> to <2 x i8>
123+
; SPV-DAG: Select [[vec_16]] [[s6]] [[zeros_1]] [[mones_16]] [[zeros_16]]
124+
; LLVM-DAG: %s6 = select <2 x i1> zeroinitializer, <2 x i16> <i16 -1, i16 -1>, <2 x i16> zeroinitializer
125+
%s6 = sext <2 x i1> <i1 0, i1 0> to <2 x i16>
126+
; SPV-DAG: Select [[vec_32]] [[s7]] [[false_true]] [[mones_32]] [[zeros_32]]
127+
; LLVM-DAG: %s7 = select <2 x i1> <i1 false, i1 true>, <2 x i32> <i32 -1, i32 -1>, <2 x i32> zeroinitializer
128+
%s7 = sext <2 x i1> <i1 0, i1 1> to <2 x i32>
129+
; SPV-DAG: Select [[vec_64]] [[s8]] [[ones_1]] [[mones_64]] [[zeros_64]]
130+
; LLVM-DAG: %s8 = select <2 x i1> <i1 true, i1 true>, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
131+
%s8 = sext <2 x i1> <i1 1, i1 1> to <2 x i64>
132+
; SPV-DAG: Select [[int_8]] [[z1]] [[true]] [[one_8]] [[zero_8]]
133+
; LLVM-DAG: %z1 = select i1 true, i8 1, i8 0
134+
%z1 = zext i1 1 to i8
135+
; SPV-DAG: Select [[int_16]] [[z2]] [[false]] [[one_16]] [[zero_16]]
136+
; LLVM-DAG: %z2 = select i1 false, i16 1, i16 0
137+
%z2 = zext i1 0 to i16
138+
; SPV-DAG: Select [[int_32]] [[z3]] [[true]] [[one_32]] [[zero_32]]
139+
; LLVM-DAG: %z3 = select i1 true, i32 1, i32 0
140+
%z3 = zext i1 1 to i32
141+
; SPV-DAG: Select [[int_64]] [[z4]] [[true]] [[one_64]] [[zero_64]]
142+
; LLVM-DAG: %z4 = select i1 true, i64 1, i64 0
143+
%z4 = zext i1 1 to i64
144+
; SPV-DAG: Select [[vec_8]] [[z5]] [[true_false]] [[ones_8]] [[zeros_8]]
145+
; LLVM-DAG: %z5 = select <2 x i1> <i1 true, i1 false>, <2 x i8> <i8 1, i8 1>, <2 x i8> zeroinitializer
146+
%z5 = zext <2 x i1> <i1 1, i1 0> to <2 x i8>
147+
; SPV-DAG: Select [[vec_16]] [[z6]] [[zeros_1]] [[ones_16]] [[zeros_16]]
148+
; LLVM-DAG: %z6 = select <2 x i1> zeroinitializer, <2 x i16> <i16 1, i16 1>, <2 x i16> zeroinitializer
149+
%z6 = zext <2 x i1> <i1 0, i1 0> to <2 x i16>
150+
; SPV-DAG: Select [[vec_32]] [[z7]] [[false_true]] [[ones_32]] [[zeros_32]]
151+
; LLVM-DAG: %z7 = select <2 x i1> <i1 false, i1 true>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
152+
%z7 = zext <2 x i1> <i1 0, i1 1> to <2 x i32>
153+
; SPV-DAG: Select [[vec_64]] [[z8]] [[ones_1]] [[ones_64]] [[zeros_64]]
154+
; LLVM-DAG: %z8 = select <2 x i1> <i1 true, i1 true>, <2 x i64> <i64 1, i64 1>, <2 x i64> zeroinitializer
155+
%z8 = zext <2 x i1> <i1 1, i1 1> to <2 x i64>
156+
; SPV-DAG: Select [[int_32]] [[ufp1_res:[0-9]+]] [[true]] [[one_32]] [[zero_32]]
157+
; SPV-DAG: ConvertUToF [[float]] [[ufp1]] [[ufp1_res]]
158+
; LLVM-DAG: %[[ufp1_res_llvm:[0-9]+]] = select i1 true, i32 1, i32 0
159+
; LLVM-DAG: %ufp1 = uitofp i32 %[[ufp1_res_llvm]] to float
160+
%ufp1 = uitofp i1 1 to float
161+
; SPV-DAG: Select [[vec_32]] [[ufp2_res:[0-9]+]] [[true_false]] [[ones_32]] [[zeros_32]]
162+
; SPV-DAG: ConvertUToF [[vec_float]] [[ufp2]] [[ufp2_res]]
163+
; LLVM-DAG: %[[ufp2_res_llvm:[0-9]+]] = select <2 x i1> <i1 true, i1 false>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
164+
; LLVM-DAG: %ufp2 = uitofp <2 x i32> %[[ufp2_res_llvm]] to <2 x float>
165+
%ufp2 = uitofp <2 x i1> <i1 1, i1 0> to <2 x float>
166+
; SPV-DAG: Select [[int_32]] [[sfp1_res:[0-9]+]] [[true]] [[one_32]] [[zero_32]]
167+
; SPV-DAG: ConvertSToF [[float]] [[sfp1]] [[sfp1_res]]
168+
; LLVM-DAG: %[[sfp1_res_llvm:[0-9]+]] = select i1 true, i32 1, i32 0
169+
; LLVM-DAG: %sfp1 = sitofp i32 %[[sfp1_res_llvm:[0-9]+]] to float
170+
%sfp1 = sitofp i1 1 to float
171+
; SPV-DAG: Select [[vec_32]] [[sfp2_res:[0-9]+]] [[true_false]] [[ones_32]] [[zeros_32]]
172+
; SPV-DAG: ConvertSToF [[vec_float]] [[sfp2]] [[sfp2_res]]
173+
; LLVM-DAG: %[[sfp2_res_llvm:[0-9]+]] = select <2 x i1> <i1 true, i1 false>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
174+
; LLVM-DAG: %sfp2 = sitofp <2 x i32> %[[sfp2_res_llvm]] to <2 x float>
175+
%sfp2 = sitofp <2 x i1> <i1 1, i1 0> to <2 x float>
37176
ret void
38177
}
39178

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