@@ -1433,7 +1433,7 @@ SPIRVInstruction *LLVMToSPIRVBase::transCmpInst(CmpInst *Cmp,
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SPIRVValue *LLVMToSPIRVBase::transUnaryInst (UnaryInstruction *U,
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SPIRVBasicBlock *BB) {
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- if (isa<BitCastInst>(U) && U->getType ()->isPointerTy ()) {
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+ if (isa<BitCastInst>(U) && U->getType ()->isPtrOrPtrVectorTy ()) {
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if (isa<ConstantPointerNull>(U->getOperand (0 ))) {
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SPIRVType *ExpectedTy = transScavengedType (U);
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return BM->addNullConstant (bcast<SPIRVTypePointer>(ExpectedTy));
@@ -1799,7 +1799,7 @@ SPIRVValue *LLVMToSPIRVBase::transAtomicLoad(LoadInst *LD,
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std::vector<SPIRVValue *> SPIRVOps = transValue (Ops, BB);
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return mapValue (LD, BM->addInstTemplate (OpAtomicLoad, BM->getIds (SPIRVOps),
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- BB, transType (LD-> getType () )));
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+ BB, transScavengedType (LD)));
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}
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// Aliasing list MD contains several scope MD nodes whithin it. Each scope MD
@@ -1878,9 +1878,9 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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// Though variables with common linkage type are initialized by 0,
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// they can be represented in SPIR-V as uninitialized variables with
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// 'Export' linkage type, just as tentative definitions look in C
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- llvm::Value *Init = GV->hasInitializer () && !GV->hasCommonLinkage ()
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- ? GV->getInitializer ()
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- : nullptr ;
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+ llvm::Constant *Init = GV->hasInitializer () && !GV->hasCommonLinkage ()
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+ ? GV->getInitializer ()
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+ : nullptr ;
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SPIRVValue *BVarInit = nullptr ;
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StructType *ST = Init ? dyn_cast<StructType>(Init->getType ()) : nullptr ;
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if (ST && ST->hasName () && isSPIRVConstantName (ST->getName ())) {
@@ -1927,10 +1927,8 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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}
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}
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}
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- // As global variables define a pointer to their "content" type, we should
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- // translate here only pointer without declaration even if it is a
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- // function pointer.
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- BVarInit = transValue (Init, nullptr , true , FuncTransMode::Pointer);
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+ SPIRVType *TransTy = transType (Ty);
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+ BVarInit = transConstantUse (Init, TransTy->getPointerElementType ());
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}
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SPIRVStorageClassKind StorageClass;
@@ -2235,7 +2233,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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if (auto Ext = dyn_cast<ExtractValueInst>(V)) {
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return mapValue (V, BM->addCompositeExtractInst (
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- transType (Ext-> getType () ),
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+ transScavengedType (Ext),
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transValue (Ext->getAggregateOperand (), BB),
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Ext->getIndices (), BB));
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}
@@ -2303,7 +2301,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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auto Index = Ext->getIndexOperand ();
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if (auto Const = dyn_cast<ConstantInt>(Index))
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return mapValue (V, BM->addCompositeExtractInst (
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- transType (Ext-> getType () ),
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+ transScavengedType (Ext),
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transValue (Ext->getVectorOperand (), BB),
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std::vector<SPIRVWord>(1 , Const->getZExtValue ()),
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BB));
@@ -2334,7 +2332,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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for (auto &I : SF->getShuffleMask ())
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Comp.push_back (I);
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return mapValue (V, BM->addVectorShuffleInst (
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- transType (SF-> getType () ),
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+ transScavengedType (SF),
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transValue (SF->getOperand (0 ), BB),
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transValue (SF->getOperand (1 ), BB), Comp, BB));
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}
@@ -2367,7 +2365,7 @@ LLVMToSPIRVBase::transValueWithoutDecoration(Value *V, SPIRVBasicBlock *BB,
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Operands[3 ] = ARMW->getValOperand ();
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std::vector<SPIRVValue *> OpVals = transValue (Operands, BB);
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std::vector<SPIRVId> Ops = BM->getIds (OpVals);
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- SPIRVType *Ty = transType (ARMW-> getType () );
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+ SPIRVType *Ty = transScavengedType (ARMW);
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spv::Op OC;
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if (Op == AtomicRMWInst::FSub) {
@@ -4015,7 +4013,7 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
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case Intrinsic::dbg_value:
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return DbgTran->createDebugValuePlaceholder (cast<DbgValueInst>(II), BB);
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case Intrinsic::annotation: {
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- SPIRVType *Ty = transType (II-> getType () );
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+ SPIRVType *Ty = transScavengedType (II);
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GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(II->getArgOperand (1 ));
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if (!GEP)
@@ -4082,8 +4080,7 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
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// Translate FPGARegIntel annotations to OpFPGARegINTEL.
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if (AnnotationString == kOCLBuiltinName ::FPGARegIntel) {
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- // TODO: Check for opaque pointer requirements.
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- auto *Ty = transType (II->getType ());
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+ auto *Ty = transScavengedType (II);
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auto *BI = dyn_cast<BitCastInst>(II->getOperand (0 ));
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if (BM->isAllowedToUseExtension (ExtensionID::SPV_INTEL_fpga_reg))
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return BM->addFPGARegINTELInst (Ty, transValue (BI, BB), BB);
@@ -4228,7 +4225,7 @@ SPIRVValue *LLVMToSPIRVBase::transIntrinsicInst(IntrinsicInst *II,
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" -spirv-allow-unknown-intrinsics option." );
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return nullptr ;
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}
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- SPIRVType *Ty = transType (II-> getType () );
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+ SPIRVType *Ty = transScavengedType (II);
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auto *PtrVector = transValue (II->getArgOperand (0 ), BB);
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uint32_t Alignment =
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cast<ConstantInt>(II->getArgOperand (1 ))->getZExtValue ();
@@ -5808,7 +5805,7 @@ LLVMToSPIRVBase::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
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}
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default : {
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if (isCvtOpCode (OC) && OC != OpGenericCastToPtrExplicit) {
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- return BM->addUnaryInst (OC, transType (CI-> getType () ),
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+ return BM->addUnaryInst (OC, transScavengedType (CI),
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transValue (CI->getArgOperand (0 ), BB), BB);
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} else if (isCmpOpCode (OC) || isUnaryPredicateOpCode (OC)) {
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auto ResultTy = CI->getType ();
@@ -5838,12 +5835,12 @@ LLVMToSPIRVBase::transBuiltinToInstWithoutDecoration(Op OC, CallInst *CI,
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return BM->addSelectInst (Res, One, Zero, BB);
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} else if (isBinaryOpCode (OC)) {
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assert (CI && CI->arg_size () == 2 && " Invalid call inst" );
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- return BM->addBinaryInst (OC, transType (CI-> getType () ),
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+ return BM->addBinaryInst (OC, transScavengedType (CI),
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transValue (CI->getArgOperand (0 ), BB),
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transValue (CI->getArgOperand (1 ), BB), BB);
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} else if (CI->arg_size () == 1 && !CI->getType ()->isVoidTy () &&
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!hasExecScope (OC) && !isAtomicOpCode (OC)) {
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- return BM->addUnaryInst (OC, transType (CI-> getType () ),
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+ return BM->addUnaryInst (OC, transScavengedType (CI),
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transValue (CI->getArgOperand (0 ), BB), BB);
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} else {
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auto Args = getArguments (CI);
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