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aratajewsvenvh
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Fix SPIRV-IR for group opcodes
1 parent ddb5c96 commit 9a81ba8

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6 files changed

+665
-70
lines changed

6 files changed

+665
-70
lines changed

lib/SPIRV/SPIRVUtil.cpp

Lines changed: 63 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1665,6 +1665,69 @@ class SPIRVFriendlyIRMangleInfo : public BuiltinFuncMangleInfo {
16651665
addUnsignedArg(0);
16661666
addUnsignedArg(3);
16671667
break;
1668+
case OpGroupUMax:
1669+
LLVM_FALLTHROUGH;
1670+
case OpGroupUMin:
1671+
LLVM_FALLTHROUGH;
1672+
case OpGroupNonUniformBroadcast:
1673+
LLVM_FALLTHROUGH;
1674+
case OpGroupNonUniformBallotBitCount:
1675+
LLVM_FALLTHROUGH;
1676+
case OpGroupNonUniformShuffle:
1677+
LLVM_FALLTHROUGH;
1678+
case OpGroupNonUniformShuffleXor:
1679+
LLVM_FALLTHROUGH;
1680+
case OpGroupNonUniformShuffleUp:
1681+
LLVM_FALLTHROUGH;
1682+
case OpGroupNonUniformShuffleDown:
1683+
addUnsignedArg(2);
1684+
break;
1685+
case OpGroupNonUniformInverseBallot:
1686+
LLVM_FALLTHROUGH;
1687+
case OpGroupNonUniformBallotFindLSB:
1688+
LLVM_FALLTHROUGH;
1689+
case OpGroupNonUniformBallotFindMSB:
1690+
addUnsignedArg(1);
1691+
break;
1692+
case OpGroupNonUniformBallotBitExtract:
1693+
addUnsignedArg(1);
1694+
addUnsignedArg(2);
1695+
break;
1696+
case OpGroupNonUniformIAdd:
1697+
LLVM_FALLTHROUGH;
1698+
case OpGroupNonUniformFAdd:
1699+
LLVM_FALLTHROUGH;
1700+
case OpGroupNonUniformIMul:
1701+
LLVM_FALLTHROUGH;
1702+
case OpGroupNonUniformFMul:
1703+
LLVM_FALLTHROUGH;
1704+
case OpGroupNonUniformSMin:
1705+
LLVM_FALLTHROUGH;
1706+
case OpGroupNonUniformFMin:
1707+
LLVM_FALLTHROUGH;
1708+
case OpGroupNonUniformSMax:
1709+
LLVM_FALLTHROUGH;
1710+
case OpGroupNonUniformFMax:
1711+
LLVM_FALLTHROUGH;
1712+
case OpGroupNonUniformBitwiseAnd:
1713+
LLVM_FALLTHROUGH;
1714+
case OpGroupNonUniformBitwiseOr:
1715+
LLVM_FALLTHROUGH;
1716+
case OpGroupNonUniformBitwiseXor:
1717+
LLVM_FALLTHROUGH;
1718+
case OpGroupNonUniformLogicalAnd:
1719+
LLVM_FALLTHROUGH;
1720+
case OpGroupNonUniformLogicalOr:
1721+
LLVM_FALLTHROUGH;
1722+
case OpGroupNonUniformLogicalXor:
1723+
addUnsignedArg(3);
1724+
break;
1725+
case OpGroupNonUniformUMax:
1726+
LLVM_FALLTHROUGH;
1727+
case OpGroupNonUniformUMin:
1728+
addUnsignedArg(2);
1729+
addUnsignedArg(3);
1730+
break;
16681731
default:;
16691732
// No special handling is needed
16701733
}

test/GroupAndSubgroupInstructions.spvasm

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -79,10 +79,10 @@
7979
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupIAddiii(i32, i32, i32) #[[#Attrs]]
8080
; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFAddiif(i32, i32, float) #[[#Attrs]]
8181
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupSMiniii(i32, i32, i32) #[[#Attrs]]
82-
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMiniii(i32, i32, i32) #[[#Attrs]]
82+
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMiniij(i32, i32, i32) #[[#Attrs]]
8383
; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFMiniif(i32, i32, float) #[[#Attrs]]
8484
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupSMaxiii(i32, i32, i32) #[[#Attrs]]
85-
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMaxiii(i32, i32, i32) #[[#Attrs]]
85+
; CHECK-SPV-IR: declare spir_func i32 @_Z17__spirv_GroupUMaxiij(i32, i32, i32) #[[#Attrs]]
8686
; CHECK-SPV-IR: declare spir_func float @_Z17__spirv_GroupFMaxiif(i32, i32, float) #[[#Attrs]]
8787
; CHECK-SPV-IR: declare spir_func i32 @_Z23intel_sub_group_shuffleij(i32, i32) #[[#Attrs]]
8888
; CHECK-SPV-IR: declare spir_func i32 @_Z28intel_sub_group_shuffle_downiij(i32, i32, i32) #[[#Attrs]]

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