@@ -168,6 +168,96 @@ for.end36: ; preds = %for.cond29
168
168
ret void
169
169
}
170
170
171
+ ; Function Attrs: convergent norecurse nounwind mustprogress
172
+ define linkonce_odr dso_local spir_func void @_Z18loop_count_controlILi12EEvv () #0 {
173
+ entry:
174
+ %a = alloca [10 x i32 ], align 4
175
+ %a.ascast = addrspacecast [10 x i32 ]* %a to [10 x i32 ] addrspace (4 )*
176
+ %i = alloca i32 , align 4
177
+ %i.ascast = addrspacecast i32* %i to i32 addrspace (4 )*
178
+ %cleanup.dest.slot = alloca i32 , align 4
179
+ %i1 = alloca i32 , align 4
180
+ %i1.ascast = addrspacecast i32* %i1 to i32 addrspace (4 )*
181
+ %cleanup.dest.slot5 = alloca i32 , align 4
182
+ %0 = bitcast [10 x i32 ]* %a to i8*
183
+ call void @llvm.lifetime.start.p0i8 (i64 40 , i8* %0 )
184
+ %1 = bitcast i32* %i to i8*
185
+ call void @llvm.lifetime.start.p0i8 (i64 4 , i8* %1 )
186
+ store i32 0 , i32 addrspace (4 )* %i.ascast , align 4
187
+ br label %for.cond
188
+ ; Per SPIR-V spec extension INTEL/SPV_INTEL_fpga_loop_controls,
189
+ ; LoopControlLoopCountINTELMask = 0x1000000 (16777216)
190
+ ; CHECK-SPIRV: LoopMerge [[#]] [[#]] 16777216 4294967295 4294967295 4294967295 4294967295 12 0
191
+ ; CHECK-SPIRV-NEXT: BranchConditional [[#]] [[#]] [[#]]
192
+ ; CHECK-SPIRV-NEGATIVE-NOT: LoopMerge [[#]] [[#]] 16777216
193
+ for.cond: ; preds = %for.inc, %entry
194
+ %2 = load i32 , i32 addrspace (4 )* %i.ascast , align 4
195
+ %cmp = icmp ne i32 %2 , 10
196
+ br i1 %cmp , label %for.body , label %for.cond.cleanup
197
+
198
+ for.cond.cleanup: ; preds = %for.cond
199
+ %3 = bitcast i32* %i to i8*
200
+ call void @llvm.lifetime.end.p0i8 (i64 4 , i8* %3 )
201
+ br label %for.end
202
+
203
+ for.body: ; preds = %for.cond
204
+ %4 = load i32 , i32 addrspace (4 )* %i.ascast , align 4
205
+ %idxprom = sext i32 %4 to i64
206
+ %arrayidx = getelementptr inbounds [10 x i32 ], [10 x i32 ] addrspace (4 )* %a.ascast , i64 0 , i64 %idxprom
207
+ store i32 0 , i32 addrspace (4 )* %arrayidx , align 4
208
+ br label %for.inc
209
+
210
+ for.inc: ; preds = %for.body
211
+ %5 = load i32 , i32 addrspace (4 )* %i.ascast , align 4
212
+ %inc = add nsw i32 %5 , 1
213
+ store i32 %inc , i32 addrspace (4 )* %i.ascast , align 4
214
+ br label %for.cond , !llvm.loop !12
215
+
216
+ for.end: ; preds = %for.cond.cleanup
217
+ %6 = bitcast i32* %i1 to i8*
218
+ call void @llvm.lifetime.start.p0i8 (i64 4 , i8* %6 )
219
+ store i32 0 , i32 addrspace (4 )* %i1.ascast , align 4
220
+ br label %for.cond2
221
+
222
+ ; Per SPIR-V spec extension INTEL/SPV_INTEL_fpga_loop_controls,
223
+ ; spv::internal::LoopControlLoopCountINTELMask = 0x1000000 (16777216)
224
+ ; Parameters 4 0 = 4, 100 1 = 4294967396, 21 0 = 21
225
+ ; CHECK-SPIRV: LoopMerge [[#]] [[#]] 16777216 4 0 100 1 21 0
226
+ ; CHECK-SPIRV-NEXT: BranchConditional [[#]] [[#]] [[#]]
227
+ ; CHECK-SPIRV-NEGATIVE-NOT: LoopMerge [[#]] [[#]] 16777216
228
+ for.cond2: ; preds = %for.inc9, %for.end
229
+ %7 = load i32 , i32 addrspace (4 )* %i1.ascast , align 4
230
+ %cmp3 = icmp ne i32 %7 , 10
231
+ br i1 %cmp3 , label %for.body6 , label %for.cond.cleanup4
232
+
233
+ for.cond.cleanup4: ; preds = %for.cond2
234
+ %8 = bitcast i32* %i1 to i8*
235
+ call void @llvm.lifetime.end.p0i8 (i64 4 , i8* %8 )
236
+ br label %for.end11
237
+
238
+ for.body6: ; preds = %for.cond2
239
+ %9 = load i32 , i32 addrspace (4 )* %i1.ascast , align 4
240
+ %idxprom7 = sext i32 %9 to i64
241
+ %arrayidx8 = getelementptr inbounds [10 x i32 ], [10 x i32 ] addrspace (4 )* %a.ascast , i64 0 , i64 %idxprom7
242
+ store i32 0 , i32 addrspace (4 )* %arrayidx8 , align 4
243
+ br label %for.inc9
244
+
245
+ for.inc9: ; preds = %for.body6
246
+ %10 = load i32 , i32 addrspace (4 )* %i1.ascast , align 4
247
+ %inc10 = add nsw i32 %10 , 1
248
+ store i32 %inc10 , i32 addrspace (4 )* %i1.ascast , align 4
249
+ br label %for.cond2 , !llvm.loop !15
250
+
251
+ for.end11: ; preds = %for.cond.cleanup4
252
+ %11 = bitcast [10 x i32 ]* %a to i8*
253
+ call void @llvm.lifetime.end.p0i8 (i64 40 , i8* %11 )
254
+ ret void
255
+ }
256
+
257
+ declare void @llvm.lifetime.start.p0i8 (i64 immarg, i8* nocapture )
258
+
259
+ declare void @llvm.lifetime.end.p0i8 (i64 immarg, i8* nocapture )
260
+
171
261
attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math" ="false" "denorms-are-zero" ="false" "disable-tail-calls" ="false" "less-precise-fpmad" ="false" "min-legal-vector-width" ="0" "no-frame-pointer-elim" ="false" "no-infs-fp-math" ="false" "no-jump-tables" ="false" "no-nans-fp-math" ="false" "no-signed-zeros-fp-math" ="false" "no-trapping-math" ="false" "stack-protector-buffer-size" ="8" "uniform-work-group-size" ="true" "unsafe-fp-math" ="false" "use-soft-float" ="false" }
172
262
173
263
!llvm.module.flags = !{!0 }
@@ -186,12 +276,22 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
186
276
!9 = distinct !{!9 , !10 }
187
277
!10 = !{!"llvm.loop.max_concurrency.count" , i32 2 }
188
278
!11 = distinct !{!11 , !8 , !10 }
279
+ !12 = distinct !{!12 , !13 , !14 }
280
+ !13 = !{!"llvm.loop.mustprogress" }
281
+ !14 = !{!"llvm.loop.intel.loopcount_avg" , i64 12 }
282
+ !15 = distinct !{!15 , !13 , !16 , !17 , !18 }
283
+ !16 = !{!"llvm.loop.intel.loopcount_min" , i64 4 }
284
+ ;4294967396 = 2^32 + 100
285
+ !17 = !{!"llvm.loop.intel.loopcount_max" , i64 4294967396 }
286
+ !18 = !{!"llvm.loop.intel.loopcount_avg" , i64 21 }
189
287
190
288
; CHECK-LLVM: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_A:[0-9]+]]
191
289
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]]
192
290
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_C:[0-9]+]]
193
291
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_D:[0-9]+]]
194
292
; CHECK-LLVM: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_E:[0-9]+]]
293
+ ; CHECK-LLVM: br label %for.cond{{.*}}, !llvm.loop ![[#MD_F:]]
294
+ ; CHECK-LLVM: br label %for.cond{{.*}}, !llvm.loop ![[#MD_G:]]
195
295
196
296
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]*}}, !llvm.loop ![[MD_A:[0-9]+]]
197
297
; CHECK-LLVM-NEGATIVE: br label %for.cond{{[0-9]+}}, !llvm.loop ![[MD_B:[0-9]+]]
@@ -206,10 +306,19 @@ attributes #0 = { convergent noinline nounwind optnone "correctly-rounded-divide
206
306
; CHECK-LLVM: ![[MD_D]] = distinct !{![[MD_D]], ![[MD_max_concurrency:[0-9]+]]}
207
307
; CHECK-LLVM: ![[MD_max_concurrency]] = !{!"llvm.loop.max_concurrency.count", i32 2}
208
308
; CHECK-LLVM: ![[MD_E]] = distinct !{![[MD_E]], ![[MD_ii:[0-9]+]], ![[MD_max_concurrency:[0-9]+]]}
309
+ ; CHECK-LLVM: ![[#MD_F]] = distinct !{![[#MD_F]], ![[#MD_loop_count_avg:]]}
310
+ ; CHECK-LLVM: ![[#MD_loop_count_avg]] = !{!"llvm.loop.intel.loopcount_avg", i64 12}
311
+ ; CHECK-LLVM: ![[#MD_G]] = distinct !{![[#MD_G]], ![[#MD_loop_count_min:]], ![[#MD_loop_count_max:]], ![[#MD_loop_count_avg_1:]]}
312
+ ; CHECK-LLVM: ![[#MD_loop_count_min]] = !{!"llvm.loop.intel.loopcount_min", i64 4}
313
+ ; CHECK-LLVM: ![[#MD_loop_count_max]] = !{!"llvm.loop.intel.loopcount_max", i64 4294967396}
314
+ ; CHECK-LLVM: ![[#MD_loop_count_avg_1]] = !{!"llvm.loop.intel.loopcount_avg", i64 21}
209
315
210
316
; CHECK-LLVM-NEGATIVE: ![[MD_A]] = distinct !{![[MD_A]], ![[MD_ivdep_enable:[0-9]+]]}
211
317
; CHECK-LLVM-NEGATIVE: ![[MD_ivdep_enable]] = !{!"llvm.loop.ivdep.enable"}
212
318
; CHECK-LLVM-NEGATIVE: ![[MD_B]] = distinct !{![[MD_B]], ![[MD_ivdep:[0-9]+]]}
213
319
; CHECK-LLVM-NEGATIVE: ![[MD_ivdep]] = !{!"llvm.loop.ivdep.safelen", i32 2}
214
320
; CHECK-LLVM-NEGATIVE-NOT: !{{.*}} = !{!"llvm.loop.ii.count"{{.*}}}
215
321
; CHECK-LLVM-NEGATIVE-NOT: !{{.*}} = !{!"llvm.loop.max_concurrency.count"{{.*}}}
322
+ ; CHECK-LLVM-NEGATIVE-NOT: !{{.*}} = !{!"llvm.loop.intel.loopcount_min"{{.*}}}
323
+ ; CHECK-LLVM-NEGATIVE-NOT: !{{.*}} = !{!"llvm.loop.intel.loopcount_max"{{.*}}}
324
+ ; CHECK-LLVM-NEGATIVE-NOT: !{{.*}} = !{!"llvm.loop.intel.loopcount_avg"{{.*}}}
0 commit comments