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svenvhAlexeySotkin
svenvh
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AlexeySotkin
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Handle OpSpecConstantOp with Select
`OpSpecConstantOp` may be used outside of a basic block (for example in a variable initializer). Modify the `SPIRVSelect` constructor to accept a `nullptr` basic block. Use an IRBuilder when translating `OpSelect`, so that the resulting select expression will be created as a constant expression (and possibly constant-folded) where possible. Update some tests as the SPIR-V to LLVM translation now folds selects more aggressively due to the use of IRBuilder.
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+92
-84
lines changed

7 files changed

+92
-84
lines changed

‎lib/SPIRV/SPIRVReader.cpp

Lines changed: 8 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1962,11 +1962,15 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
19621962

19631963
case OpSelect: {
19641964
SPIRVSelect *BS = static_cast<SPIRVSelect *>(BV);
1965+
IRBuilder<> Builder(*Context);
1966+
if (BB) {
1967+
Builder.SetInsertPoint(BB);
1968+
}
19651969
return mapValue(BV,
1966-
SelectInst::Create(transValue(BS->getCondition(), F, BB),
1967-
transValue(BS->getTrueValue(), F, BB),
1968-
transValue(BS->getFalseValue(), F, BB),
1969-
BV->getName(), BB));
1970+
Builder.CreateSelect(transValue(BS->getCondition(), F, BB),
1971+
transValue(BS->getTrueValue(), F, BB),
1972+
transValue(BS->getFalseValue(), F, BB),
1973+
BV->getName()));
19701974
}
19711975

19721976
case OpVmeImageINTEL:

‎lib/SPIRV/libSPIRV/SPIRVInstruction.cpp

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -244,8 +244,14 @@ SPIRVInstruction *createInstFromSpecConstantOp(SPIRVSpecConstantOp *Inst) {
244244
assert(isSpecConstantOpAllowedOp(OC) &&
245245
"Op code not allowed for OpSpecConstantOp");
246246
Ops.erase(Ops.begin(), Ops.begin() + 1);
247-
return SPIRVInstTemplateBase::create(OC, Inst->getType(), Inst->getId(), Ops,
248-
nullptr, Inst->getModule());
247+
switch (OC) {
248+
case OpSelect:
249+
return new SPIRVSelect(Inst->getId(), Inst->getType(), Ops[0], Ops[1],
250+
Ops[2], nullptr, Inst->getModule());
251+
default:
252+
return SPIRVInstTemplateBase::create(OC, Inst->getType(), Inst->getId(),
253+
Ops, nullptr, Inst->getModule());
254+
}
249255
}
250256

251257
} // namespace SPIRV

‎lib/SPIRV/libSPIRV/SPIRVInstruction.h

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -970,13 +970,12 @@ _SPIRV_OP(Unordered)
970970
class SPIRVSelect : public SPIRVInstruction {
971971
public:
972972
// Complete constructor
973-
SPIRVSelect(SPIRVId TheId, SPIRVId TheCondition, SPIRVId TheOp1,
974-
SPIRVId TheOp2, SPIRVBasicBlock *TheBB)
975-
: SPIRVInstruction(6, OpSelect, TheBB->getValueType(TheOp1), TheId,
976-
TheBB),
973+
SPIRVSelect(SPIRVId TheId, SPIRVType *TheType, SPIRVId TheCondition,
974+
SPIRVId TheOp1, SPIRVId TheOp2, SPIRVBasicBlock *TheBB,
975+
SPIRVModule *TheM)
976+
: SPIRVInstruction(6, OpSelect, TheType, TheId, TheBB, TheM),
977977
Condition(TheCondition), Op1(TheOp1), Op2(TheOp2) {
978978
validate();
979-
assert(TheBB && "Invalid BB");
980979
}
981980
// Incomplete constructor
982981
SPIRVSelect()

‎lib/SPIRV/libSPIRV/SPIRVModule.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1436,8 +1436,9 @@ SPIRVInstruction *SPIRVModuleImpl::addSelectInst(SPIRVValue *Condition,
14361436
SPIRVValue *Op1,
14371437
SPIRVValue *Op2,
14381438
SPIRVBasicBlock *BB) {
1439-
return addInstruction(new SPIRVSelect(getId(), Condition->getId(),
1440-
Op1->getId(), Op2->getId(), BB),
1439+
return addInstruction(new SPIRVSelect(getId(), Op1->getType(),
1440+
Condition->getId(), Op1->getId(),
1441+
Op2->getId(), BB, this),
14411442
BB);
14421443
}
14431444

‎test/SpecConstants/specconstantop-init.spvasm

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535
; CHECK: @var_lognot = addrspace(1) global i1 false
3636
; CHECK: @var_logeq = addrspace(1) global i1 false
3737
; CHECK: @var_logne = addrspace(1) global i1 true
38+
; CHECK: @var_select = addrspace(1) global i32 53
3839
; CHECK: @var_icmpeq = addrspace(1) global i1 false
3940
; CHECK: @var_icmpne = addrspace(1) global i1 true
4041
; CHECK: @var_icmpult = addrspace(1) global i1 true
@@ -80,6 +81,7 @@
8081
OpDecorate %var_lognot LinkageAttributes "var_lognot" Export
8182
OpDecorate %var_logeq LinkageAttributes "var_logeq" Export
8283
OpDecorate %var_logne LinkageAttributes "var_logne" Export
84+
OpDecorate %var_select LinkageAttributes "var_select" Export
8385
OpDecorate %var_icmpeq LinkageAttributes "var_icmpeq" Export
8486
OpDecorate %var_icmpne LinkageAttributes "var_icmpne" Export
8587
OpDecorate %var_icmpult LinkageAttributes "var_icmpult" Export
@@ -128,6 +130,7 @@
128130
%lognot = OpSpecConstantOp %bool LogicalNot %true
129131
%logeq = OpSpecConstantOp %bool LogicalEqual %true %false
130132
%logne = OpSpecConstantOp %bool LogicalNotEqual %true %false
133+
%select = OpSpecConstantOp %uint Select %logeq %uint_4 %uint_53
131134
%icmpeq = OpSpecConstantOp %bool IEqual %uint_53 %uint_min4
132135
%icmpne = OpSpecConstantOp %bool INotEqual %uint_53 %uint_min4
133136
%icmpult = OpSpecConstantOp %bool ULessThan %uint_53 %uint_min4
@@ -171,6 +174,7 @@
171174
%var_lognot = OpVariable %_ptr_bool CrossWorkgroup %lognot
172175
%var_logeq = OpVariable %_ptr_bool CrossWorkgroup %logeq
173176
%var_logne = OpVariable %_ptr_bool CrossWorkgroup %logne
177+
%var_select = OpVariable %_ptr_uint CrossWorkgroup %select
174178
%var_icmpeq = OpVariable %_ptr_bool CrossWorkgroup %icmpeq
175179
%var_icmpne = OpVariable %_ptr_bool CrossWorkgroup %icmpne
176180
%var_icmpult = OpVariable %_ptr_bool CrossWorkgroup %icmpult

‎test/transcoding/spec_const.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,10 +34,8 @@ target triple = "spir"
3434
; Function Attrs: nofree norecurse nounwind writeonly
3535
define spir_kernel void @foo(i8 addrspace(1)* nocapture %b, i8 addrspace(1)* nocapture %c, i16 addrspace(1)* nocapture %s, i32 addrspace(1)* nocapture %i, i64 addrspace(1)* nocapture %l, half addrspace(1)* nocapture %h, float addrspace(1)* nocapture %f, double addrspace(1)* nocapture %d) local_unnamed_addr #0 !kernel_arg_addr_space !3 !kernel_arg_access_qual !4 !kernel_arg_type !5 !kernel_arg_base_type !5 !kernel_arg_type_qual !6 {
3636
entry:
37-
; CHECK-LLVM: %conv = select i1 false, i8 1, i8 0
38-
; CHECK-LLVM: store i8 %conv, i8 addrspace(1)* %b, align 1
39-
; CHECK-LLVM-SPEC: %conv = select i1 true, i8 1, i8 0
40-
; CHECK-LLVM-SPEC: store i8 %conv, i8 addrspace(1)* %b, align 1
37+
; CHECK-LLVM: store i8 0, i8 addrspace(1)* %b, align 1
38+
; CHECK-LLVM-SPEC: store i8 1, i8 addrspace(1)* %b, align 1
4139
%0 = call i1 @_Z20__spirv_SpecConstantib(i32 0, i1 false)
4240
%conv = zext i1 %0 to i8
4341
store i8 %conv, i8 addrspace(1)* %b, align 1

‎test/uitofp-with-bool.ll

Lines changed: 63 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -61,20 +61,14 @@
6161
; SPV-DAG: TypeVector [[vec_32:[0-9]+]] [[int_32]] 2
6262
; SPV-DAG: TypeVector [[vec_64:[0-9]+]] [[int_64]] 2
6363
; SPV-DAG: TypeVector [[vec_float:[0-9]+]] [[float]] 2
64-
; SPV-DAG: ConstantTrue [[bool]] [[true:[0-9]+]]
65-
; SPV-DAG: ConstantFalse [[bool]] [[false:[0-9]+]]
6664
; SPV-DAG: ConstantNull [[vec_8]] [[zeros_8:[0-9]+]]
6765
; SPV-DAG: ConstantComposite [[vec_8]] [[mones_8:[0-9]+]] [[mone_8]] [[mone_8]]
68-
; SPV-DAG: ConstantComposite [[vec_1]] [[true_false:[0-9]+]] [[true]] [[false]]
6966
; SPV-DAG: ConstantNull [[vec_16]] [[zeros_16:[0-9]+]]
7067
; SPV-DAG: ConstantComposite [[vec_16]] [[mones_16:[0-9]+]] [[mone_16]] [[mone_16]]
71-
; SPV-DAG: ConstantNull [[vec_1]] [[zeros_1:[0-9]+]]
7268
; SPV-DAG: ConstantNull [[vec_32]] [[zeros_32:[0-9]+]]
7369
; SPV-DAG: ConstantComposite [[vec_32]] [[mones_32:[0-9]+]] [[mone_32]] [[mone_32]]
74-
; SPV-DAG: ConstantComposite [[vec_1]] [[false_true:[0-9]+]] [[false]] [[true]]
7570
; SPV-DAG: ConstantNull [[vec_64]] [[zeros_64:[0-9]+]]
7671
; SPV-DAG: ConstantComposite [[vec_64]] [[mones_64:[0-9]+]] [[mone_64]] [[mone_64]]
77-
; SPV-DAG: ConstantComposite [[vec_1]] [[ones_1:[0-9]+]] [[true]] [[true]]
7872
; SPV-DAG: ConstantComposite [[vec_8]] [[ones_8:[0-9]+]] [[one_8]] [[one_8]]
7973
; SPV-DAG: ConstantComposite [[vec_16]] [[ones_16:[0-9]+]] [[one_16]] [[one_16]]
8074
; SPV-DAG: ConstantComposite [[vec_32]] [[ones_32:[0-9]+]] [[one_32]] [[one_32]]
@@ -87,9 +81,11 @@ target triple = "spir64"
8781
; SPV-DAG: Function
8882
; SPV-DAG: FunctionParameter {{[0-9]+}} [[A:[0-9]+]]
8983
; SPV-DAG: FunctionParameter {{[0-9]+}} [[B:[0-9]+]]
84+
; SPV-DAG: FunctionParameter {{[0-9]+}} [[i1s:[0-9]+]]
85+
; SPV-DAG: FunctionParameter {{[0-9]+}} [[i1v:[0-9]+]]
9086

9187
; Function Attrs: nofree norecurse nounwind writeonly
92-
define dso_local spir_kernel void @K(float addrspace(1)* nocapture %A, i32 %B) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
88+
define dso_local spir_kernel void @K(float addrspace(1)* nocapture %A, i32 %B, i1 %i1s, <2 x i1> %i1v) local_unnamed_addr #0 !kernel_arg_addr_space !2 !kernel_arg_access_qual !3 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !5 {
9389
entry:
9490

9591

@@ -105,74 +101,74 @@ entry:
105101
; LLVM-DAG: store float %conv, float addrspace(1)* %A, align 4
106102
store float %conv, float addrspace(1)* %A, align 4;
107103

108-
; SPV-DAG: Select [[int_8]] [[s1]] [[true]] [[mone_8]] [[zero_8]]
109-
; LLVM-DAG: %s1 = select i1 true, i8 -1, i8 0
110-
%s1 = sext i1 1 to i8
111-
; SPV-DAG: Select [[int_16]] [[s2]] [[false]] [[mone_16]] [[zero_16]]
112-
; LLVM-DAG: %s2 = select i1 false, i16 -1, i16 0
113-
%s2 = sext i1 0 to i16
114-
; SPV-DAG: Select [[int_32]] [[s3]] [[true]] [[mone_32]] [[zero_32]]
115-
; LLVM-DAG: %s3 = select i1 true, i32 -1, i32 0
116-
%s3 = sext i1 1 to i32
117-
; SPV-DAG: Select [[int_64]] [[s4]] [[true]] [[mone_64]] [[zero_64]]
118-
; LLVM-DAG: %s4 = select i1 true, i64 -1, i64 0
119-
%s4 = sext i1 1 to i64
120-
; SPV-DAG: Select [[vec_8]] [[s5]] [[true_false]] [[mones_8]] [[zeros_8]]
121-
; LLVM-DAG: %s5 = select <2 x i1> <i1 true, i1 false>, <2 x i8> <i8 -1, i8 -1>, <2 x i8> zeroinitializer
122-
%s5 = sext <2 x i1> <i1 1, i1 0> to <2 x i8>
123-
; SPV-DAG: Select [[vec_16]] [[s6]] [[zeros_1]] [[mones_16]] [[zeros_16]]
124-
; LLVM-DAG: %s6 = select <2 x i1> zeroinitializer, <2 x i16> <i16 -1, i16 -1>, <2 x i16> zeroinitializer
125-
%s6 = sext <2 x i1> <i1 0, i1 0> to <2 x i16>
126-
; SPV-DAG: Select [[vec_32]] [[s7]] [[false_true]] [[mones_32]] [[zeros_32]]
127-
; LLVM-DAG: %s7 = select <2 x i1> <i1 false, i1 true>, <2 x i32> <i32 -1, i32 -1>, <2 x i32> zeroinitializer
128-
%s7 = sext <2 x i1> <i1 0, i1 1> to <2 x i32>
129-
; SPV-DAG: Select [[vec_64]] [[s8]] [[ones_1]] [[mones_64]] [[zeros_64]]
130-
; LLVM-DAG: %s8 = select <2 x i1> <i1 true, i1 true>, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
131-
%s8 = sext <2 x i1> <i1 1, i1 1> to <2 x i64>
132-
; SPV-DAG: Select [[int_8]] [[z1]] [[true]] [[one_8]] [[zero_8]]
133-
; LLVM-DAG: %z1 = select i1 true, i8 1, i8 0
134-
%z1 = zext i1 1 to i8
135-
; SPV-DAG: Select [[int_16]] [[z2]] [[false]] [[one_16]] [[zero_16]]
136-
; LLVM-DAG: %z2 = select i1 false, i16 1, i16 0
137-
%z2 = zext i1 0 to i16
138-
; SPV-DAG: Select [[int_32]] [[z3]] [[true]] [[one_32]] [[zero_32]]
139-
; LLVM-DAG: %z3 = select i1 true, i32 1, i32 0
140-
%z3 = zext i1 1 to i32
141-
; SPV-DAG: Select [[int_64]] [[z4]] [[true]] [[one_64]] [[zero_64]]
142-
; LLVM-DAG: %z4 = select i1 true, i64 1, i64 0
143-
%z4 = zext i1 1 to i64
144-
; SPV-DAG: Select [[vec_8]] [[z5]] [[true_false]] [[ones_8]] [[zeros_8]]
145-
; LLVM-DAG: %z5 = select <2 x i1> <i1 true, i1 false>, <2 x i8> <i8 1, i8 1>, <2 x i8> zeroinitializer
146-
%z5 = zext <2 x i1> <i1 1, i1 0> to <2 x i8>
147-
; SPV-DAG: Select [[vec_16]] [[z6]] [[zeros_1]] [[ones_16]] [[zeros_16]]
148-
; LLVM-DAG: %z6 = select <2 x i1> zeroinitializer, <2 x i16> <i16 1, i16 1>, <2 x i16> zeroinitializer
149-
%z6 = zext <2 x i1> <i1 0, i1 0> to <2 x i16>
150-
; SPV-DAG: Select [[vec_32]] [[z7]] [[false_true]] [[ones_32]] [[zeros_32]]
151-
; LLVM-DAG: %z7 = select <2 x i1> <i1 false, i1 true>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
152-
%z7 = zext <2 x i1> <i1 0, i1 1> to <2 x i32>
153-
; SPV-DAG: Select [[vec_64]] [[z8]] [[ones_1]] [[ones_64]] [[zeros_64]]
154-
; LLVM-DAG: %z8 = select <2 x i1> <i1 true, i1 true>, <2 x i64> <i64 1, i64 1>, <2 x i64> zeroinitializer
155-
%z8 = zext <2 x i1> <i1 1, i1 1> to <2 x i64>
156-
; SPV-DAG: Select [[int_32]] [[ufp1_res:[0-9]+]] [[true]] [[one_32]] [[zero_32]]
104+
; SPV-DAG: Select [[int_8]] [[s1]] [[i1s]] [[mone_8]] [[zero_8]]
105+
; LLVM-DAG: %s1 = select i1 %i1s, i8 -1, i8 0
106+
%s1 = sext i1 %i1s to i8
107+
; SPV-DAG: Select [[int_16]] [[s2]] [[i1s]] [[mone_16]] [[zero_16]]
108+
; LLVM-DAG: %s2 = select i1 %i1s, i16 -1, i16 0
109+
%s2 = sext i1 %i1s to i16
110+
; SPV-DAG: Select [[int_32]] [[s3]] [[i1s]] [[mone_32]] [[zero_32]]
111+
; LLVM-DAG: %s3 = select i1 %i1s, i32 -1, i32 0
112+
%s3 = sext i1 %i1s to i32
113+
; SPV-DAG: Select [[int_64]] [[s4]] [[i1s]] [[mone_64]] [[zero_64]]
114+
; LLVM-DAG: %s4 = select i1 %i1s, i64 -1, i64 0
115+
%s4 = sext i1 %i1s to i64
116+
; SPV-DAG: Select [[vec_8]] [[s5]] [[i1v]] [[mones_8]] [[zeros_8]]
117+
; LLVM-DAG: %s5 = select <2 x i1> %i1v, <2 x i8> <i8 -1, i8 -1>, <2 x i8> zeroinitializer
118+
%s5 = sext <2 x i1> %i1v to <2 x i8>
119+
; SPV-DAG: Select [[vec_16]] [[s6]] [[i1v]] [[mones_16]] [[zeros_16]]
120+
; LLVM-DAG: %s6 = select <2 x i1> %i1v, <2 x i16> <i16 -1, i16 -1>, <2 x i16> zeroinitializer
121+
%s6 = sext <2 x i1> %i1v to <2 x i16>
122+
; SPV-DAG: Select [[vec_32]] [[s7]] [[i1v]] [[mones_32]] [[zeros_32]]
123+
; LLVM-DAG: %s7 = select <2 x i1> %i1v, <2 x i32> <i32 -1, i32 -1>, <2 x i32> zeroinitializer
124+
%s7 = sext <2 x i1> %i1v to <2 x i32>
125+
; SPV-DAG: Select [[vec_64]] [[s8]] [[i1v]] [[mones_64]] [[zeros_64]]
126+
; LLVM-DAG: %s8 = select <2 x i1> %i1v, <2 x i64> <i64 -1, i64 -1>, <2 x i64> zeroinitializer
127+
%s8 = sext <2 x i1> %i1v to <2 x i64>
128+
; SPV-DAG: Select [[int_8]] [[z1]] [[i1s]] [[one_8]] [[zero_8]]
129+
; LLVM-DAG: %z1 = select i1 %i1s, i8 1, i8 0
130+
%z1 = zext i1 %i1s to i8
131+
; SPV-DAG: Select [[int_16]] [[z2]] [[i1s]] [[one_16]] [[zero_16]]
132+
; LLVM-DAG: %z2 = select i1 %i1s, i16 1, i16 0
133+
%z2 = zext i1 %i1s to i16
134+
; SPV-DAG: Select [[int_32]] [[z3]] [[i1s]] [[one_32]] [[zero_32]]
135+
; LLVM-DAG: %z3 = select i1 %i1s, i32 1, i32 0
136+
%z3 = zext i1 %i1s to i32
137+
; SPV-DAG: Select [[int_64]] [[z4]] [[i1s]] [[one_64]] [[zero_64]]
138+
; LLVM-DAG: %z4 = select i1 %i1s, i64 1, i64 0
139+
%z4 = zext i1 %i1s to i64
140+
; SPV-DAG: Select [[vec_8]] [[z5]] [[i1v]] [[ones_8]] [[zeros_8]]
141+
; LLVM-DAG: %z5 = select <2 x i1> %i1v, <2 x i8> <i8 1, i8 1>, <2 x i8> zeroinitializer
142+
%z5 = zext <2 x i1> %i1v to <2 x i8>
143+
; SPV-DAG: Select [[vec_16]] [[z6]] [[i1v]] [[ones_16]] [[zeros_16]]
144+
; LLVM-DAG: %z6 = select <2 x i1> %i1v, <2 x i16> <i16 1, i16 1>, <2 x i16> zeroinitializer
145+
%z6 = zext <2 x i1> %i1v to <2 x i16>
146+
; SPV-DAG: Select [[vec_32]] [[z7]] [[i1v]] [[ones_32]] [[zeros_32]]
147+
; LLVM-DAG: %z7 = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
148+
%z7 = zext <2 x i1> %i1v to <2 x i32>
149+
; SPV-DAG: Select [[vec_64]] [[z8]] [[i1v]] [[ones_64]] [[zeros_64]]
150+
; LLVM-DAG: %z8 = select <2 x i1> %i1v, <2 x i64> <i64 1, i64 1>, <2 x i64> zeroinitializer
151+
%z8 = zext <2 x i1> %i1v to <2 x i64>
152+
; SPV-DAG: Select [[int_32]] [[ufp1_res:[0-9]+]] [[i1s]] [[one_32]] [[zero_32]]
157153
; SPV-DAG: ConvertUToF [[float]] [[ufp1]] [[ufp1_res]]
158-
; LLVM-DAG: %[[ufp1_res_llvm:[0-9]+]] = select i1 true, i32 1, i32 0
154+
; LLVM-DAG: %[[ufp1_res_llvm:[0-9]+]] = select i1 %i1s, i32 1, i32 0
159155
; LLVM-DAG: %ufp1 = uitofp i32 %[[ufp1_res_llvm]] to float
160-
%ufp1 = uitofp i1 1 to float
161-
; SPV-DAG: Select [[vec_32]] [[ufp2_res:[0-9]+]] [[true_false]] [[ones_32]] [[zeros_32]]
156+
%ufp1 = uitofp i1 %i1s to float
157+
; SPV-DAG: Select [[vec_32]] [[ufp2_res:[0-9]+]] [[i1v]] [[ones_32]] [[zeros_32]]
162158
; SPV-DAG: ConvertUToF [[vec_float]] [[ufp2]] [[ufp2_res]]
163-
; LLVM-DAG: %[[ufp2_res_llvm:[0-9]+]] = select <2 x i1> <i1 true, i1 false>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
159+
; LLVM-DAG: %[[ufp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
164160
; LLVM-DAG: %ufp2 = uitofp <2 x i32> %[[ufp2_res_llvm]] to <2 x float>
165-
%ufp2 = uitofp <2 x i1> <i1 1, i1 0> to <2 x float>
166-
; SPV-DAG: Select [[int_32]] [[sfp1_res:[0-9]+]] [[true]] [[one_32]] [[zero_32]]
161+
%ufp2 = uitofp <2 x i1> %i1v to <2 x float>
162+
; SPV-DAG: Select [[int_32]] [[sfp1_res:[0-9]+]] [[i1s]] [[one_32]] [[zero_32]]
167163
; SPV-DAG: ConvertSToF [[float]] [[sfp1]] [[sfp1_res]]
168-
; LLVM-DAG: %[[sfp1_res_llvm:[0-9]+]] = select i1 true, i32 1, i32 0
164+
; LLVM-DAG: %[[sfp1_res_llvm:[0-9]+]] = select i1 %i1s, i32 1, i32 0
169165
; LLVM-DAG: %sfp1 = sitofp i32 %[[sfp1_res_llvm:[0-9]+]] to float
170-
%sfp1 = sitofp i1 1 to float
171-
; SPV-DAG: Select [[vec_32]] [[sfp2_res:[0-9]+]] [[true_false]] [[ones_32]] [[zeros_32]]
166+
%sfp1 = sitofp i1 %i1s to float
167+
; SPV-DAG: Select [[vec_32]] [[sfp2_res:[0-9]+]] [[i1v]] [[ones_32]] [[zeros_32]]
172168
; SPV-DAG: ConvertSToF [[vec_float]] [[sfp2]] [[sfp2_res]]
173-
; LLVM-DAG: %[[sfp2_res_llvm:[0-9]+]] = select <2 x i1> <i1 true, i1 false>, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
169+
; LLVM-DAG: %[[sfp2_res_llvm:[0-9]+]] = select <2 x i1> %i1v, <2 x i32> <i32 1, i32 1>, <2 x i32> zeroinitializer
174170
; LLVM-DAG: %sfp2 = sitofp <2 x i32> %[[sfp2_res_llvm]] to <2 x float>
175-
%sfp2 = sitofp <2 x i1> <i1 1, i1 0> to <2 x float>
171+
%sfp2 = sitofp <2 x i1> %i1v to <2 x float>
176172
ret void
177173
}
178174

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