[X86] SkylakeClientModel - fix instregex typo. NFCI.

RKSimon · RKSimon · commit 1dd0613810ff · 2022-11-08T18:40:23.000Z
The extra '?' is useless as it only makes a single letter optional and we can only match the SI64 pattern anyway (V?)CVT(T?)SS2SIrr has a different scheduler def
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -1149,7 +1149,7 @@ def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
   let NumMicroOps = 3;
   let ResourceCycles = [1,1,1];
 }
-def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64?rr")>;
+def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;
 
 def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
   let Latency = 7;

Original file line number	Diff line number	Diff line change
`@@ -1149,7 +1149,7 @@ def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {`
`1149`	`1149`	`let NumMicroOps = 3;`
`1150`	`1150`	`let ResourceCycles = [1,1,1];`
`1151`	`1151`	`}`
`1152`		`-def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64?rr")>;`
	`1152`	`+def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>;`
`1153`	`1153`
`1154`	`1154`	`def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {`
`1155`	`1155`	`let Latency = 7;`