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AMDGPU: Add baseline test for broken machine sinking
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‎llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 < %s | FileCheck %s
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; A VGPR loop variable was incorrectly sunk into a flow block, past
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; the si_end_cf reconvergence point.
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define void @machinesink_loop_variable_out_of_divergent_loop(i32 %arg, i1 %cmp49280.not, i32 %arg1, i1 %cmp108) {
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; CHECK-LABEL: machinesink_loop_variable_out_of_divergent_loop:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v1, 1, v1
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; CHECK-NEXT: v_and_b32_e32 v3, 1, v3
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; CHECK-NEXT: s_mov_b32 s5, 0
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; CHECK-NEXT: v_cmp_eq_u32_e64 s4, 1, v1
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v3
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; CHECK-NEXT: s_xor_b32 s6, s4, -1
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; CHECK-NEXT: s_inst_prefetch 0x1
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; CHECK-NEXT: s_branch .LBB0_3
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; CHECK-NEXT: .p2align 6
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; CHECK-NEXT: .LBB0_1: ; %Flow
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; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s8
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; CHECK-NEXT: v_add_nc_u32_e32 v4, -4, v4
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; CHECK-NEXT: .LBB0_2: ; %Flow1
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; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s7
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; CHECK-NEXT: v_cmp_ne_u32_e64 s4, 0, v3
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; j lastloop entry
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: s_or_b32 s5, s4, s5
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; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s5
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; CHECK-NEXT: s_cbranch_execz .LBB0_8
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; CHECK-NEXT: .LBB0_3: ; %for.body33
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; CHECK-NEXT: ; =>This Loop Header: Depth=1
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; CHECK-NEXT: ; Child Loop BB0_6 Depth 2
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: s_and_saveexec_b32 s7, s6
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; CHECK-NEXT: s_cbranch_execz .LBB0_2
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; CHECK-NEXT: ; %bb.4: ; %for.body51.preheader
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; CHECK-NEXT: ; in Loop: Header=BB0_3 Depth=1
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; CHECK-NEXT: s_mov_b32 s8, 0
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; CHECK-NEXT: s_mov_b32 s9, 0
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; CHECK-NEXT: s_branch .LBB0_6
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; CHECK-NEXT: .p2align 6
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; CHECK-NEXT: .LBB0_5: ; %if.end118
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; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; CHECK-NEXT: s_add_i32 s9, s9, 4
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; CHECK-NEXT: ;;#ASMSTART
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; CHECK-NEXT: ; backedge
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; CHECK-NEXT: ;;#ASMEND
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; CHECK-NEXT: v_add_nc_u32_e32 v4, s9, v2
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; CHECK-NEXT: v_cmp_ge_u32_e64 s4, v4, v0
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; CHECK-NEXT: s_or_b32 s8, s4, s8
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; CHECK-NEXT: s_andn2_b32 exec_lo, exec_lo, s8
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; CHECK-NEXT: s_cbranch_execz .LBB0_1
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; CHECK-NEXT: .LBB0_6: ; %for.body51
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; CHECK-NEXT: ; Parent Loop BB0_3 Depth=1
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; CHECK-NEXT: ; => This Inner Loop Header: Depth=2
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; CHECK-NEXT: v_mov_b32_e32 v3, 1
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; CHECK-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; CHECK-NEXT: s_cbranch_execz .LBB0_5
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; CHECK-NEXT: ; %bb.7: ; %if.then112
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; CHECK-NEXT: ; in Loop: Header=BB0_6 Depth=2
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; CHECK-NEXT: s_add_i32 s10, s9, 4
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: v_mov_b32_e32 v4, s10
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; CHECK-NEXT: ds_write_b32 v1, v4
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; CHECK-NEXT: s_branch .LBB0_5
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; CHECK-NEXT: .LBB0_8: ; %for.body159.preheader
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; CHECK-NEXT: s_inst_prefetch 0x2
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s5
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; CHECK-NEXT: s_mov_b32 vcc_lo, exec_lo
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; CHECK-NEXT: .LBB0_9: ; %for.body159
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_cbranch_vccnz .LBB0_9
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; CHECK-NEXT: ; %bb.10: ; %DummyReturnBlock
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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entry:
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br label %for.body33
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for.body33: ; preds = %for.end121, %entry
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br i1 %cmp49280.not, label %for.end121, label %for.body51
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for.body51: ; preds = %if.end118, %for.body33
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%add48284 = phi i32 [ %add48, %if.end118 ], [ %arg1, %for.body33 ]
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%collision.0281 = phi i32 [ %inc119, %if.end118 ], [ 1, %for.body33 ]
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br i1 %cmp108, label %if.then112, label %if.end118
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if.then112: ; preds = %for.body51
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%inc101 = add i32 %collision.0281, 3
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store i32 %inc101, ptr addrspace(3) null, align 2147483648
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br label %if.end118
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if.end118: ; preds = %if.then112, %for.body51
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%thCollNum.5 = phi i32 [ 0, %if.then112 ], [ 1, %for.body51 ]
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%inc119 = add i32 %collision.0281, 4
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tail call void asm sideeffect "; backedge", ""()
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%add48 = add i32 %add48284, 4
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%cmp49 = icmp ult i32 %add48, %arg
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br i1 %cmp49, label %for.body51, label %for.end121
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for.end121: ; preds = %if.end118, %for.body33
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%thCollNum.1.lcssa = phi i32 [ 0, %for.body33 ], [ %thCollNum.5, %if.end118 ]
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%j.0.lcssa = phi i32 [ 0, %for.body33 ], [ %add48284, %if.end118 ]
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%i5 = tail call i32 asm sideeffect "; j lastloop entry", "=v,0"(i32 %j.0.lcssa)
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%cmp31 = icmp eq i32 %thCollNum.1.lcssa, 0
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br i1 %cmp31, label %for.body33, label %for.body159
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for.body159: ; preds = %for.body159, %for.end121
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br label %for.body159
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}

‎llvm/test/CodeGen/AMDGPU/machine-sink-loop-var-out-of-divergent-loop-swdev407790.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -run-pass=machine-sink -o - %s | FileCheck %s
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# A VGPR loop variable was incorrectly sunk into a flow block, past
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# the si_end_cf reconvergence point.
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---
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name: machinesink_loop_vgpr_out_of_divergent_loop
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; CHECK-LABEL: name: machinesink_loop_vgpr_out_of_divergent_loop
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $sgpr8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[COPY1]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF [[COPY1]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
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; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_32 = SI_IF_BREAK killed [[SI_IF1]], [[SI_IF]], implicit-def dead $scc
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; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.4
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; CHECK-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, implicit [[V_ADD_U32_e64_]]
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.7(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SI_LOOP [[SI_IF]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7:
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; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc
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; CHECK-NEXT: S_BRANCH %bb.8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.8:
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; CHECK-NEXT: SI_RETURN
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bb.0:
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liveins: $vgpr0, $vgpr1, $sgpr8
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%0:vgpr_32 = COPY $vgpr0
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%1:sreg_32 = COPY $sgpr8
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%2:vgpr_32 = COPY $vgpr1
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bb.1:
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%3:sreg_32 = SI_IF %1, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:sreg_32 = SI_IF %1, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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S_NOP 0
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bb.4:
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INLINEASM &"", 1 /* sideeffect attdialect */
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%5:vgpr_32 = V_ADD_U32_e64 %0, %1, 0, implicit $exec
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%6:sreg_32 = SI_IF_BREAK killed %4, %3, implicit-def dead $scc
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SI_LOOP %6, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.5
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bb.5:
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%7:vgpr_32 = PHI %0, %bb.4
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SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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INLINEASM &"", 1, implicit %5
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S_BRANCH %bb.2
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bb.6:
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SI_LOOP %3, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.7
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bb.7:
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S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc
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S_BRANCH %bb.8
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bb.8:
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SI_RETURN
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...
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# The same testcase, except the relevant instruction is scalar and
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# could be legally sunk.
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---
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name: machinesink_loop_sgpr_out_of_divergent_loop
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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; CHECK-LABEL: name: machinesink_loop_sgpr_out_of_divergent_loop
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; CHECK: bb.0:
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; CHECK-NEXT: successors: %bb.1(0x80000000)
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; CHECK-NEXT: liveins: $sgpr8, $sgpr9, $sgpr10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr8
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr9
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.1:
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; CHECK-NEXT: successors: %bb.6(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32 = SI_IF [[COPY1]], %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2:
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; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF [[COPY1]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.3:
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; CHECK-NEXT: successors: %bb.4(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_NOP 0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.4:
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; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.5(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
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; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_32 = SI_IF_BREAK killed [[SI_IF1]], [[SI_IF]], implicit-def dead $scc
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; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.5
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.5:
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; CHECK-NEXT: successors: %bb.2(0x80000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.4
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; CHECK-NEXT: SI_END_CF [[SI_IF_BREAK]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def dead $scc
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; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */, implicit [[S_ADD_I32_]]
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; CHECK-NEXT: S_BRANCH %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.6:
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; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.7(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: SI_LOOP [[SI_IF]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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; CHECK-NEXT: S_BRANCH %bb.7
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.7:
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; CHECK-NEXT: successors: %bb.7(0x40000000), %bb.8(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc
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; CHECK-NEXT: S_BRANCH %bb.8
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.8:
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; CHECK-NEXT: SI_RETURN
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bb.0:
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liveins: $sgpr8, $sgpr9, $sgpr10
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%0:sreg_32 = COPY $sgpr8
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%1:sreg_32 = COPY $sgpr9
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%2:sreg_32 = COPY $sgpr10
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bb.1:
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%3:sreg_32 = SI_IF %1, %bb.6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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%4:sreg_32 = SI_IF %1, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.3
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198+
bb.3:
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S_NOP 0
200+
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bb.4:
202+
INLINEASM &"", 1 /* sideeffect attdialect */
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%5:sreg_32 = S_ADD_I32 %0, %1, implicit-def dead $scc
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%6:sreg_32 = SI_IF_BREAK killed %4, %3, implicit-def dead $scc
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SI_LOOP %6, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.5
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bb.5:
209+
%7:vgpr_32 = PHI %0, %bb.4
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SI_END_CF %6, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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INLINEASM &"", 1, implicit %5
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S_BRANCH %bb.2
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bb.6:
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SI_LOOP %3, %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
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S_BRANCH %bb.7
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bb.7:
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S_CBRANCH_VCCNZ %bb.7, implicit undef $vcc
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S_BRANCH %bb.8
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bb.8:
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SI_RETURN
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...

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