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docs/build/arm64-windows-abi-conventions.md

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description: "Learn more about: Overview of ARM64 ABI conventions"
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title: "Overview of ARM64 ABI conventions"
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ms.date: "03/27/2019"
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ms.date: 03/25/2025
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---
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# Overview of ARM64 ABI conventions
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## Floating-point exceptions
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Support for IEEE floating-point exceptions on AArch64 systems is optional. This can be verified by writing a value that enables exceptions to the `FPCR` register and then reading it back. The bits corresponding to supported exceptions will remain set, while the bits corresponding to unsupported exceptions will be reset by the CPU.
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Most ARM hardware doesn't support IEEE floating-point exceptions. You can determine if an ARM CPU supports them by writing a value that enables exceptions to the FPCR register and then reading it back. If the CPU supports floating-point exceptions, the bits corresponding to supported exceptions will remain set, while the bits corresponding to unsupported exceptions will be reset by the CPU.
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For ARM CPUs that do support IEEE floating-point exceptions, the behavior on Windows is as follows:
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- **Windows ARM ABI**: The Windows kernel silently catches these exceptions and implicitly disables them in the FPSCR register. This approach ensures normalized behavior across processor variants, preventing unexpected exceptions when code developed on a platform without exception support runs on a platform with support.
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- **Windows ARM64 ABI**: For processor variants that support hardware floating-point exceptions, the Windows kernel catches these exceptions and disables them in the FPCR register. This ensures consistent behavior across different processor variants.
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- The [`_set_controlfp`](/cpp/c-runtime-library/reference/controlfp-s) function on ARM platforms correctly changes the FPCR register when unmasking floating-point exceptions. However, instead of raising an unmasked exception, Windows resets the FPCR register to its defaults every time an FP exception is about to be raised.
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## Parameter passing
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