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1 parent 63ceb9a commit 7198b8aCopy full SHA for 7198b8a
llvm/test/CodeGen/X86/x86-64-extend-shift.ll
@@ -1,10 +1,15 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
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; Formerly there were two shifts.
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define i64 @baz(i32 %A) nounwind {
-; CHECK: shlq $49, %r
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- %tmp1 = shl i32 %A, 17
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- %tmp2 = zext i32 %tmp1 to i64
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- %tmp3 = shl i64 %tmp2, 32
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- ret i64 %tmp3
+; CHECK-LABEL: baz:
+; CHECK: ## %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlq $49, %rax
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+; CHECK-NEXT: retq
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+ %tmp1 = shl i32 %A, 17
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+ %tmp2 = zext i32 %tmp1 to i64
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+ %tmp3 = shl i64 %tmp2, 32
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+ ret i64 %tmp3
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}
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