Skip to content

Commit 0b01944

Browse files
pravinjagtappravinjagtap
committed
[AMDGPU] Support FAdd/FSub global atomics in AMDGPUAtomicOptimizer.
Reduction and Scan are implemented using `Iterative` and `DPP` strategy for `float` type. Reviewed By: arsenm, #amdgpu Differential Revision: https://reviews.llvm.org/D156301 Change-Id: I945ebc1ba3f1a3af34f498aafe2553d195da20f0
1 parent 25171dd commit 0b01944

18 files changed

+3251
-771
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp

Lines changed: 138 additions & 66 deletions
Large diffs are not rendered by default.

‎llvm/test/CodeGen/AMDGPU/GlobalISel/atomic_optimizations_mul_one.ll

Lines changed: 55 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1+
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
22
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
33
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-atomic-optimizer %s | FileCheck -check-prefix=IR %s
44
; RUN: llc -global-isel -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
@@ -9,29 +9,31 @@ declare i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32, <4 x i32>, i32, i32,
99
declare void @llvm.amdgcn.struct.buffer.store.format.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32 immarg)
1010

1111
define amdgpu_cs void @atomic_add(<4 x i32> inreg %arg) {
12-
; IR-LABEL: @atomic_add(
12+
; IR-LABEL: define amdgpu_cs void @atomic_add
13+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
1314
; IR-NEXT: .entry:
1415
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
15-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
16-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
17-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
18-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
16+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
17+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
18+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
19+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
1920
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
2021
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
2122
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
2223
; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
2324
; IR-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
2425
; IR: 9:
25-
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
26+
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
2627
; IR-NEXT: br label [[TMP11]]
2728
; IR: 11:
2829
; IR-NEXT: ret void
2930
;
3031
; GCN-LABEL: atomic_add:
3132
; GCN: ; %bb.0: ; %.entry
3233
; GCN-NEXT: s_mov_b64 s[4:5], exec
34+
; GCN-NEXT: s_mov_b32 s6, s5
3335
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
34-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
36+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s6, v0
3537
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
3638
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
3739
; GCN-NEXT: s_cbranch_execz .LBB0_2
@@ -48,20 +50,21 @@ define amdgpu_cs void @atomic_add(<4 x i32> inreg %arg) {
4850
}
4951

5052
define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
51-
; IR-LABEL: @atomic_add_and_format(
53+
; IR-LABEL: define amdgpu_cs void @atomic_add_and_format
54+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
5255
; IR-NEXT: .entry:
5356
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
54-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
55-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
56-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
57-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
57+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
58+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
59+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
60+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
5861
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
5962
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
6063
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
6164
; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
6265
; IR-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
6366
; IR: 9:
64-
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
67+
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.add.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
6568
; IR-NEXT: br label [[TMP11]]
6669
; IR: 11:
6770
; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], [[TMP9]] ]
@@ -73,8 +76,9 @@ define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
7376
; GCN-LABEL: atomic_add_and_format:
7477
; GCN: ; %bb.0: ; %.entry
7578
; GCN-NEXT: s_mov_b64 s[6:7], exec
79+
; GCN-NEXT: s_mov_b32 s4, s7
7680
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
77-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
81+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s4, v0
7882
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
7983
; GCN-NEXT: ; implicit-def: $vgpr1
8084
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -103,29 +107,31 @@ define amdgpu_cs void @atomic_add_and_format(<4 x i32> inreg %arg) {
103107
}
104108

105109
define amdgpu_cs void @atomic_sub(<4 x i32> inreg %arg) {
106-
; IR-LABEL: @atomic_sub(
110+
; IR-LABEL: define amdgpu_cs void @atomic_sub
111+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
107112
; IR-NEXT: .entry:
108113
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
109-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
110-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
111-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
112-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
114+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
115+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
116+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
117+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
113118
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
114119
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
115120
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
116121
; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
117122
; IR-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
118123
; IR: 9:
119-
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
124+
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
120125
; IR-NEXT: br label [[TMP11]]
121126
; IR: 11:
122127
; IR-NEXT: ret void
123128
;
124129
; GCN-LABEL: atomic_sub:
125130
; GCN: ; %bb.0: ; %.entry
126131
; GCN-NEXT: s_mov_b64 s[4:5], exec
132+
; GCN-NEXT: s_mov_b32 s6, s5
127133
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
128-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
134+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s6, v0
129135
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
130136
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
131137
; GCN-NEXT: s_cbranch_execz .LBB2_2
@@ -142,20 +148,21 @@ define amdgpu_cs void @atomic_sub(<4 x i32> inreg %arg) {
142148
}
143149

144150
define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
145-
; IR-LABEL: @atomic_sub_and_format(
151+
; IR-LABEL: define amdgpu_cs void @atomic_sub_and_format
152+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
146153
; IR-NEXT: .entry:
147154
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
148-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
149-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
150-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
151-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
155+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
156+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
157+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
158+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
152159
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
153160
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
154161
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
155162
; IR-NEXT: [[TMP8:%.*]] = icmp eq i32 [[TMP5]], 0
156163
; IR-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP11:%.*]]
157164
; IR: 9:
158-
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
165+
; IR-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.sub.i32(i32 [[TMP7]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
159166
; IR-NEXT: br label [[TMP11]]
160167
; IR: 11:
161168
; IR-NEXT: [[TMP12:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP10]], [[TMP9]] ]
@@ -167,8 +174,9 @@ define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
167174
; GCN-LABEL: atomic_sub_and_format:
168175
; GCN: ; %bb.0: ; %.entry
169176
; GCN-NEXT: s_mov_b64 s[6:7], exec
177+
; GCN-NEXT: s_mov_b32 s4, s7
170178
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
171-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
179+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s4, v0
172180
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
173181
; GCN-NEXT: ; implicit-def: $vgpr1
174182
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
@@ -197,30 +205,32 @@ define amdgpu_cs void @atomic_sub_and_format(<4 x i32> inreg %arg) {
197205
}
198206

199207
define amdgpu_cs void @atomic_xor(<4 x i32> inreg %arg) {
200-
; IR-LABEL: @atomic_xor(
208+
; IR-LABEL: define amdgpu_cs void @atomic_xor
209+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
201210
; IR-NEXT: .entry:
202211
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
203-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
204-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
205-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
206-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
212+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
213+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
214+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
215+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
207216
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
208217
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
209218
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
210219
; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1
211220
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
212221
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
213222
; IR: 10:
214-
; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
223+
; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
215224
; IR-NEXT: br label [[TMP12]]
216225
; IR: 12:
217226
; IR-NEXT: ret void
218227
;
219228
; GCN-LABEL: atomic_xor:
220229
; GCN: ; %bb.0: ; %.entry
221230
; GCN-NEXT: s_mov_b64 s[4:5], exec
231+
; GCN-NEXT: s_mov_b32 s6, s5
222232
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0
223-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0
233+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s6, v0
224234
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
225235
; GCN-NEXT: s_and_saveexec_b64 s[6:7], vcc
226236
; GCN-NEXT: s_cbranch_execz .LBB4_2
@@ -238,21 +248,22 @@ define amdgpu_cs void @atomic_xor(<4 x i32> inreg %arg) {
238248
}
239249

240250
define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
241-
; IR-LABEL: @atomic_xor_and_format(
251+
; IR-LABEL: define amdgpu_cs void @atomic_xor_and_format
252+
; IR-SAME: (<4 x i32> inreg [[ARG:%.*]]) {
242253
; IR-NEXT: .entry:
243254
; IR-NEXT: [[TMP0:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
244-
; IR-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <2 x i32>
245-
; IR-NEXT: [[TMP2:%.*]] = extractelement <2 x i32> [[TMP1]], i32 0
246-
; IR-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP1]], i32 1
247-
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP2]], i32 0)
255+
; IR-NEXT: [[TMP1:%.*]] = trunc i64 [[TMP0]] to i32
256+
; IR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP0]], 32
257+
; IR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i32
258+
; IR-NEXT: [[TMP4:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP1]], i32 0)
248259
; IR-NEXT: [[TMP5:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP3]], i32 [[TMP4]])
249260
; IR-NEXT: [[TMP6:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP0]])
250261
; IR-NEXT: [[TMP7:%.*]] = trunc i64 [[TMP6]] to i32
251262
; IR-NEXT: [[TMP8:%.*]] = and i32 [[TMP7]], 1
252263
; IR-NEXT: [[TMP9:%.*]] = icmp eq i32 [[TMP5]], 0
253264
; IR-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP12:%.*]]
254265
; IR: 10:
255-
; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG:%.*]], i32 0, i32 0, i32 0, i32 0)
266+
; IR-NEXT: [[TMP11:%.*]] = call i32 @llvm.amdgcn.struct.buffer.atomic.xor.i32(i32 [[TMP8]], <4 x i32> [[ARG]], i32 0, i32 0, i32 0, i32 0)
256267
; IR-NEXT: br label [[TMP12]]
257268
; IR: 12:
258269
; IR-NEXT: [[TMP13:%.*]] = phi i32 [ poison, [[DOTENTRY:%.*]] ], [ [[TMP11]], [[TMP10]] ]
@@ -265,8 +276,9 @@ define amdgpu_cs void @atomic_xor_and_format(<4 x i32> inreg %arg) {
265276
; GCN-LABEL: atomic_xor_and_format:
266277
; GCN: ; %bb.0: ; %.entry
267278
; GCN-NEXT: s_mov_b64 s[6:7], exec
279+
; GCN-NEXT: s_mov_b32 s4, s7
268280
; GCN-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0
269-
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0
281+
; GCN-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s4, v0
270282
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
271283
; GCN-NEXT: ; implicit-def: $vgpr1
272284
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc

0 commit comments

Comments
 (0)