[AMDGPU] Add i1 mul patterns (llvm#67291)

i1 muls can sometimes happen after SCEV. They resulted in ISel failures
because we were missing the patterns for them.

Solves SWDEV-423354

Change-Id: I84457f4c2b2880d657738e91ae68871143f34a48

Author: Pierre-vh

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -744,6 +744,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
                       MVT::i8},
                      Custom);
 
+  setOperationAction(ISD::MUL, MVT::i1, Promote);
+
   setTargetDAGCombine({ISD::ADD,
                        ISD::ADDCARRY,
                        ISD::SUB,