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[CodeGen] change prototype of regalloc filter function
change the prototype of the filter function so that we can filter not just by RegClass. We need to implement more complicated filter based upon some other info associated with each register. Patch provided by: Gang Chen ([email protected]) Change-Id: Ic3b63316207d9ca75c08d085fcf88f73e8fbc8d2
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11 files changed

+64
-55
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11 files changed

+64
-55
lines changed

‎llvm/include/llvm/CodeGen/Passes.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -200,20 +200,20 @@ namespace llvm {
200200
/// possible. It is best suited for debug code where live ranges are short.
201201
///
202202
FunctionPass *createFastRegisterAllocator();
203-
FunctionPass *createFastRegisterAllocator(RegClassFilterFunc F,
203+
FunctionPass *createFastRegisterAllocator(RegAllocFilterFunc F,
204204
bool ClearVirtRegs);
205205

206206
/// BasicRegisterAllocation Pass - This pass implements a degenerate global
207207
/// register allocator using the basic regalloc framework.
208208
///
209209
FunctionPass *createBasicRegisterAllocator();
210-
FunctionPass *createBasicRegisterAllocator(RegClassFilterFunc F);
210+
FunctionPass *createBasicRegisterAllocator(RegAllocFilterFunc F);
211211

212212
/// Greedy register allocation pass - This pass implements a global register
213213
/// allocator for optimized builds.
214214
///
215215
FunctionPass *createGreedyRegisterAllocator();
216-
FunctionPass *createGreedyRegisterAllocator(RegClassFilterFunc F);
216+
FunctionPass *createGreedyRegisterAllocator(RegAllocFilterFunc F);
217217

218218
/// PBQPRegisterAllocation Pass - This pass implements the Partitioned Boolean
219219
/// Quadratic Prograaming (PBQP) based register allocator.

‎llvm/include/llvm/CodeGen/RegAllocCommon.h

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,23 +9,26 @@
99
#ifndef LLVM_CODEGEN_REGALLOCCOMMON_H
1010
#define LLVM_CODEGEN_REGALLOCCOMMON_H
1111

12+
#include "llvm/CodeGen/Register.h"
1213
#include <functional>
1314

1415
namespace llvm {
1516

1617
class TargetRegisterClass;
1718
class TargetRegisterInfo;
19+
class MachineRegisterInfo;
1820

1921
typedef std::function<bool(const TargetRegisterInfo &TRI,
20-
const TargetRegisterClass &RC)> RegClassFilterFunc;
22+
const MachineRegisterInfo &MRI, const Register Reg)>
23+
RegAllocFilterFunc;
2124

2225
/// Default register class filter function for register allocation. All virtual
2326
/// registers should be allocated.
2427
static inline bool allocateAllRegClasses(const TargetRegisterInfo &,
25-
const TargetRegisterClass &) {
28+
const MachineRegisterInfo &,
29+
const Register) {
2630
return true;
2731
}
28-
2932
}
3033

3134
#endif // LLVM_CODEGEN_REGALLOCCOMMON_H

‎llvm/lib/CodeGen/RegAllocBase.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -181,8 +181,7 @@ void RegAllocBase::enqueue(const LiveInterval *LI) {
181181
if (VRM->hasPhys(Reg))
182182
return;
183183

184-
const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
185-
if (ShouldAllocateClass(*TRI, RC)) {
184+
if (shouldAllocateRegister(Reg)) {
186185
LLVM_DEBUG(dbgs() << "Enqueuing " << printReg(Reg, TRI) << '\n');
187186
enqueueImpl(LI);
188187
} else {

‎llvm/lib/CodeGen/RegAllocBase.h

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -68,22 +68,27 @@ class RegAllocBase {
6868
LiveIntervals *LIS = nullptr;
6969
LiveRegMatrix *Matrix = nullptr;
7070
RegisterClassInfo RegClassInfo;
71-
const RegClassFilterFunc ShouldAllocateClass;
71+
const RegAllocFilterFunc shouldAllocateRegisterImpl;
7272

7373
/// Inst which is a def of an original reg and whose defs are already all
7474
/// dead after remat is saved in DeadRemats. The deletion of such inst is
7575
/// postponed till all the allocations are done, so its remat expr is
7676
/// always available for the remat of all the siblings of the original reg.
7777
SmallPtrSet<MachineInstr *, 32> DeadRemats;
7878

79-
RegAllocBase(const RegClassFilterFunc F = allocateAllRegClasses) :
80-
ShouldAllocateClass(F) {}
79+
RegAllocBase(const RegAllocFilterFunc F = allocateAllRegClasses)
80+
: shouldAllocateRegisterImpl(F) {}
8181

8282
virtual ~RegAllocBase() = default;
8383

8484
// A RegAlloc pass should call this before allocatePhysRegs.
8585
void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
8686

87+
/// Get whether a given register should be allocated.
88+
bool shouldAllocateRegister(Register Reg) {
89+
return shouldAllocateRegisterImpl(*TRI, *MRI, Reg);
90+
}
91+
8792
// The top-level driver. The output is a VirtRegMap that us updated with
8893
// physical register assignments.
8994
void allocatePhysRegs();

‎llvm/lib/CodeGen/RegAllocBasic.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -74,7 +74,7 @@ class RABasic : public MachineFunctionPass,
7474
void LRE_WillShrinkVirtReg(Register) override;
7575

7676
public:
77-
RABasic(const RegClassFilterFunc F = allocateAllRegClasses);
77+
RABasic(const RegAllocFilterFunc F = allocateAllRegClasses);
7878

7979
/// Return the pass name.
8080
StringRef getPassName() const override { return "Basic Register Allocator"; }
@@ -168,10 +168,8 @@ void RABasic::LRE_WillShrinkVirtReg(Register VirtReg) {
168168
enqueue(&LI);
169169
}
170170

171-
RABasic::RABasic(RegClassFilterFunc F):
172-
MachineFunctionPass(ID),
173-
RegAllocBase(F) {
174-
}
171+
RABasic::RABasic(RegAllocFilterFunc F)
172+
: MachineFunctionPass(ID), RegAllocBase(F) {}
175173

176174
void RABasic::getAnalysisUsage(AnalysisUsage &AU) const {
177175
AU.setPreservesCFG();
@@ -334,6 +332,6 @@ FunctionPass* llvm::createBasicRegisterAllocator() {
334332
return new RABasic();
335333
}
336334

337-
FunctionPass* llvm::createBasicRegisterAllocator(RegClassFilterFunc F) {
335+
FunctionPass *llvm::createBasicRegisterAllocator(RegAllocFilterFunc F) {
338336
return new RABasic(F);
339337
}

‎llvm/lib/CodeGen/RegAllocFast.cpp

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -178,9 +178,9 @@ class RegAllocFast : public MachineFunctionPass {
178178
public:
179179
static char ID;
180180

181-
RegAllocFast(const RegClassFilterFunc F = allocateAllRegClasses,
181+
RegAllocFast(const RegAllocFilterFunc F = allocateAllRegClasses,
182182
bool ClearVirtRegs_ = true)
183-
: MachineFunctionPass(ID), ShouldAllocateClass(F),
183+
: MachineFunctionPass(ID), shouldAllocateRegisterImpl(F),
184184
StackSlotForVirtReg(-1), ClearVirtRegs(ClearVirtRegs_) {}
185185

186186
private:
@@ -189,7 +189,7 @@ class RegAllocFast : public MachineFunctionPass {
189189
const TargetRegisterInfo *TRI = nullptr;
190190
const TargetInstrInfo *TII = nullptr;
191191
RegisterClassInfo RegClassInfo;
192-
const RegClassFilterFunc ShouldAllocateClass;
192+
const RegAllocFilterFunc shouldAllocateRegisterImpl;
193193

194194
/// Basic block currently being allocated.
195195
MachineBasicBlock *MBB = nullptr;
@@ -514,8 +514,7 @@ INITIALIZE_PASS(RegAllocFast, "regallocfast", "Fast Register Allocator", false,
514514

515515
bool RegAllocFast::shouldAllocateRegister(const Register Reg) const {
516516
assert(Reg.isVirtual());
517-
const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
518-
return ShouldAllocateClass(*TRI, RC);
517+
return shouldAllocateRegisterImpl(*TRI, *MRI, Reg);
519518
}
520519

521520
void RegAllocFast::setPhysRegState(MCPhysReg PhysReg, unsigned NewState) {
@@ -2007,7 +2006,7 @@ bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) {
20072006

20082007
FunctionPass *llvm::createFastRegisterAllocator() { return new RegAllocFast(); }
20092008

2010-
FunctionPass *llvm::createFastRegisterAllocator(RegClassFilterFunc Ftor,
2009+
FunctionPass *llvm::createFastRegisterAllocator(RegAllocFilterFunc Ftor,
20112010
bool ClearVirtRegs) {
20122011
return new RegAllocFast(Ftor, ClearVirtRegs);
20132012
}

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -192,14 +192,12 @@ FunctionPass* llvm::createGreedyRegisterAllocator() {
192192
return new RAGreedy();
193193
}
194194

195-
FunctionPass *llvm::createGreedyRegisterAllocator(RegClassFilterFunc Ftor) {
195+
FunctionPass *llvm::createGreedyRegisterAllocator(RegAllocFilterFunc Ftor) {
196196
return new RAGreedy(Ftor);
197197
}
198198

199-
RAGreedy::RAGreedy(RegClassFilterFunc F):
200-
MachineFunctionPass(ID),
201-
RegAllocBase(F) {
202-
}
199+
RAGreedy::RAGreedy(RegAllocFilterFunc F)
200+
: MachineFunctionPass(ID), RegAllocBase(F) {}
203201

204202
void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
205203
AU.setPreservesCFG();
@@ -2306,9 +2304,9 @@ void RAGreedy::tryHintRecoloring(const LiveInterval &VirtReg) {
23062304
if (Reg.isPhysical())
23072305
continue;
23082306

2309-
// This may be a skipped class
2307+
// This may be a skipped register.
23102308
if (!VRM->hasPhys(Reg)) {
2311-
assert(!ShouldAllocateClass(*TRI, *MRI->getRegClass(Reg)) &&
2309+
assert(!shouldAllocateRegister(Reg) &&
23122310
"We have an unallocated variable which should have been handled");
23132311
continue;
23142312
}
@@ -2698,7 +2696,7 @@ bool RAGreedy::hasVirtRegAlloc() {
26982696
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
26992697
if (!RC)
27002698
continue;
2701-
if (ShouldAllocateClass(*TRI, *RC))
2699+
if (shouldAllocateRegister(Reg))
27022700
return true;
27032701
}
27042702

‎llvm/lib/CodeGen/RegAllocGreedy.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,7 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
281281
bool ReverseLocalAssignment = false;
282282

283283
public:
284-
RAGreedy(const RegClassFilterFunc F = allocateAllRegClasses);
284+
RAGreedy(const RegAllocFilterFunc F = allocateAllRegClasses);
285285

286286
/// Return the pass name.
287287
StringRef getPassName() const override { return "Greedy Register Allocator"; }

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -82,16 +82,19 @@ class VGPRRegisterRegAlloc : public RegisterRegAllocBase<VGPRRegisterRegAlloc> {
8282
};
8383

8484
static bool onlyAllocateSGPRs(const TargetRegisterInfo &TRI,
85-
const TargetRegisterClass &RC) {
86-
return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
85+
const MachineRegisterInfo &MRI,
86+
const Register Reg) {
87+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
88+
return static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC);
8789
}
8890

8991
static bool onlyAllocateVGPRs(const TargetRegisterInfo &TRI,
90-
const TargetRegisterClass &RC) {
91-
return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(&RC);
92+
const MachineRegisterInfo &MRI,
93+
const Register Reg) {
94+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
95+
return !static_cast<const SIRegisterInfo &>(TRI).isSGPRClass(RC);
9296
}
9397

94-
9598
/// -{sgpr|vgpr}-regalloc=... command line option.
9699
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
97100

‎llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -277,22 +277,24 @@ class RVVRegisterRegAlloc : public RegisterRegAllocBase<RVVRegisterRegAlloc> {
277277
};
278278

279279
static bool onlyAllocateRVVReg(const TargetRegisterInfo &TRI,
280-
const TargetRegisterClass &RC) {
281-
return RISCV::VRRegClass.hasSubClassEq(&RC) ||
282-
RISCV::VRM2RegClass.hasSubClassEq(&RC) ||
283-
RISCV::VRM4RegClass.hasSubClassEq(&RC) ||
284-
RISCV::VRM8RegClass.hasSubClassEq(&RC) ||
285-
RISCV::VRN2M1RegClass.hasSubClassEq(&RC) ||
286-
RISCV::VRN2M2RegClass.hasSubClassEq(&RC) ||
287-
RISCV::VRN2M4RegClass.hasSubClassEq(&RC) ||
288-
RISCV::VRN3M1RegClass.hasSubClassEq(&RC) ||
289-
RISCV::VRN3M2RegClass.hasSubClassEq(&RC) ||
290-
RISCV::VRN4M1RegClass.hasSubClassEq(&RC) ||
291-
RISCV::VRN4M2RegClass.hasSubClassEq(&RC) ||
292-
RISCV::VRN5M1RegClass.hasSubClassEq(&RC) ||
293-
RISCV::VRN6M1RegClass.hasSubClassEq(&RC) ||
294-
RISCV::VRN7M1RegClass.hasSubClassEq(&RC) ||
295-
RISCV::VRN8M1RegClass.hasSubClassEq(&RC);
280+
const MachineRegisterInfo &MRI,
281+
const Register Reg) {
282+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
283+
return RISCV::VRRegClass.hasSubClassEq(RC) ||
284+
RISCV::VRM2RegClass.hasSubClassEq(RC) ||
285+
RISCV::VRM4RegClass.hasSubClassEq(RC) ||
286+
RISCV::VRM8RegClass.hasSubClassEq(RC) ||
287+
RISCV::VRN2M1RegClass.hasSubClassEq(RC) ||
288+
RISCV::VRN2M2RegClass.hasSubClassEq(RC) ||
289+
RISCV::VRN2M4RegClass.hasSubClassEq(RC) ||
290+
RISCV::VRN3M1RegClass.hasSubClassEq(RC) ||
291+
RISCV::VRN3M2RegClass.hasSubClassEq(RC) ||
292+
RISCV::VRN4M1RegClass.hasSubClassEq(RC) ||
293+
RISCV::VRN4M2RegClass.hasSubClassEq(RC) ||
294+
RISCV::VRN5M1RegClass.hasSubClassEq(RC) ||
295+
RISCV::VRN6M1RegClass.hasSubClassEq(RC) ||
296+
RISCV::VRN7M1RegClass.hasSubClassEq(RC) ||
297+
RISCV::VRN8M1RegClass.hasSubClassEq(RC);
296298
}
297299

298300
static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }

‎llvm/lib/Target/X86/X86TargetMachine.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -646,8 +646,10 @@ std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
646646
}
647647

648648
static bool onlyAllocateTileRegisters(const TargetRegisterInfo &TRI,
649-
const TargetRegisterClass &RC) {
650-
return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(&RC);
649+
const MachineRegisterInfo &MRI,
650+
const Register Reg) {
651+
const TargetRegisterClass *RC = MRI.getRegClass(Reg);
652+
return static_cast<const X86RegisterInfo &>(TRI).isTileRegisterClass(RC);
651653
}
652654

653655
bool X86PassConfig::addRegAssignAndRewriteOptimized() {

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