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authored and
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Avoid module pass assert when compiling for O0
Change-Id: Ife52a918a9f9e7ba4980168693a2dbffb13e6e87
1 parent 8d00d9c commit 1bd16cf

13 files changed

+243
-120
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1258,6 +1258,14 @@ bool AMDGPUAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
12581258
void AMDGPUAsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const {
12591259
AU.addRequired<AMDGPUResourceUsageAnalysis>();
12601260
AU.addPreserved<AMDGPUResourceUsageAnalysis>();
1261+
1262+
// The Dummy pass is necessary because AMDGPUResourceUsageAnalysis will pop
1263+
// the CGSCC pass manager off of the active pass managers stack. Adding the
1264+
// Dummy pass will re-insert the CGSCC pass manager into said stack again
1265+
// through CallGraphSCCPass::assignPassManager.
1266+
AU.addRequired<DummyCGSCCPass>();
1267+
AU.addPreserved<DummyCGSCCPass>();
1268+
12611269
AsmPrinter::getAnalysisUsage(AU);
12621270
}
12631271

‎llvm/lib/Target/AMDGPU/AMDGPUResourceUsageAnalysis.cpp

Lines changed: 10 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -151,9 +151,16 @@ bool AMDGPUResourceUsageAnalysis::runOnModule(Module &M) {
151151

152152
SIFunctionResourceInfo &Info = CI.first->second;
153153
MachineFunction *MF = MMI.getMachineFunction(*F);
154-
assert(MF && "function must have been generated already");
155-
Info = analyzeResourceUsage(*MF, TM);
156-
HasIndirectCall |= Info.HasIndirectCall;
154+
// We can only analyze resource usage of functions for which there exists a
155+
// machinefunction equivalent. These may not exist as the (codegen) passes
156+
// prior to this one are run in CGSCC order which will bypass any local
157+
// functions that aren't called.
158+
assert((MF || TPC->requiresCodeGenSCCOrder()) &&
159+
"function must have been generated already");
160+
if (MF) {
161+
Info = analyzeResourceUsage(*MF, TM);
162+
HasIndirectCall |= Info.HasIndirectCall;
163+
}
157164
}
158165

159166
if (HasIndirectCall)

‎llvm/test/CodeGen/AMDGPU/call-to-kernel-undefined.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=GCN %s
22
; GCN: callee_kernel:
33
; GCN: s_endpgm
4+
; GCN: __amdgpu_callee_kernel_kernel_body
5+
; GCN: s_setpc_b64
46
define amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out) #0 {
57
entry:
68
store volatile i32 0, i32 addrspace(1)* %out
@@ -13,8 +15,6 @@ entry:
1315
; GCN: s_addc_u32 s[[HI2:[0-9]+]], s[[HI1]], __amdgpu_callee_kernel_kernel_body@rel32@hi+12
1416
; GCN: s_swappc_b64 s[{{[0-9:]+}}], s{{\[}}[[LO2]]:[[HI2]]]
1517
; GCN: s_endpgm
16-
; GCN: __amdgpu_callee_kernel_kernel_body
17-
; GCN: s_setpc_b64
1818
define amdgpu_kernel void @caller_kernel(i32 addrspace(1)* %out) #0 {
1919
entry:
2020
call void @callee_kernel(i32 addrspace(1)* %out)

‎llvm/test/CodeGen/AMDGPU/call-to-kernel.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,8 @@
22

33
; GCN: callee_kernel:
44
; GCN: s_endpgm
5+
; GCN: __amdgpu_callee_kernel_kernel_body
6+
; GCN: s_setpc_b64
57
define amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out) #0 {
68
entry:
79
store volatile i32 0, i32 addrspace(1)* %out
@@ -14,8 +16,6 @@ entry:
1416
; GCN: s_addc_u32 s[[HI2:[0-9]+]], s[[HI1]], __amdgpu_callee_kernel_kernel_body@rel32@hi+12
1517
; GCN: s_swappc_b64 s[{{[0-9:]+}}], s{{\[}}[[LO2]]:[[HI2]]]
1618
; GCN: s_endpgm
17-
; GCN: __amdgpu_callee_kernel_kernel_body
18-
; GCN: s_setpc_b64
1919
define amdgpu_kernel void @caller_kernel(i32 addrspace(1)* %out) #0 {
2020
entry:
2121
call amdgpu_kernel void @callee_kernel(i32 addrspace(1)* %out)

‎llvm/test/CodeGen/AMDGPU/insert-delay-alu-bug.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,18 @@
33

44
declare i32 @llvm.amdgcn.workitem.id.x()
55

6+
define <2 x i64> @f1() #0 {
7+
; GFX11-LABEL: f1:
8+
; GFX11: ; %bb.0:
9+
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
10+
; GFX11-NEXT: v_mov_b32_e32 v0, 0
11+
; GFX11-NEXT: v_mov_b32_e32 v1, 0
12+
; GFX11-NEXT: v_mov_b32_e32 v2, 0
13+
; GFX11-NEXT: v_mov_b32_e32 v3, 0
14+
; GFX11-NEXT: s_setpc_b64 s[30:31]
15+
ret <2 x i64> zeroinitializer
16+
}
17+
618
define void @f0() {
719
; GFX11-LABEL: f0:
820
; GFX11: ; %bb.0: ; %bb
@@ -35,18 +47,6 @@ bb:
3547
ret void
3648
}
3749

38-
define <2 x i64> @f1() #0 {
39-
; GFX11-LABEL: f1:
40-
; GFX11: ; %bb.0:
41-
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
42-
; GFX11-NEXT: v_mov_b32_e32 v0, 0
43-
; GFX11-NEXT: v_mov_b32_e32 v1, 0
44-
; GFX11-NEXT: v_mov_b32_e32 v2, 0
45-
; GFX11-NEXT: v_mov_b32_e32 v3, 0
46-
; GFX11-NEXT: s_setpc_b64 s[30:31]
47-
ret <2 x i64> zeroinitializer
48-
}
49-
5050
; FIXME: This generates "instid1(/* invalid instid value */)".
5151
define amdgpu_kernel void @f2(i32 %arg, i32 %arg1, i32 %arg2, i1 %arg3, i32 %arg4, i1 %arg5, ptr %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10, i1 %arg11) {
5252
; GFX11-LABEL: f2:

‎llvm/test/CodeGen/AMDGPU/ipra.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -105,13 +105,6 @@ define void @test_funcx2() #0 {
105105
ret void
106106
}
107107

108-
; GCN-LABEL: {{^}}wombat:
109-
define weak amdgpu_kernel void @wombat(ptr %arg, ptr %arg2) {
110-
bb:
111-
call void @hoge() #0
112-
ret void
113-
}
114-
115108
; Make sure we save/restore the return address around the call.
116109
; Function Attrs: norecurse
117110
define internal void @hoge() #2 {
@@ -128,6 +121,13 @@ bb:
128121
ret void
129122
}
130123

124+
; GCN-LABEL: {{^}}wombat:
125+
define weak amdgpu_kernel void @wombat(ptr %arg, ptr %arg2) {
126+
bb:
127+
call void @hoge() #0
128+
ret void
129+
}
130+
131131
declare dso_local void @eggs()
132132

133133

‎llvm/test/CodeGen/AMDGPU/llc-pipeline.ll

Lines changed: 40 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -144,11 +144,14 @@
144144
; GCN-O0-NEXT: Machine Optimization Remark Emitter
145145
; GCN-O0-NEXT: Stack Frame Layout Analysis
146146
; GCN-O0-NEXT: Function register usage analysis
147-
; GCN-O0-NEXT: FunctionPass Manager
148-
; GCN-O0-NEXT: Lazy Machine Block Frequency Analysis
149-
; GCN-O0-NEXT: Machine Optimization Remark Emitter
150-
; GCN-O0-NEXT: AMDGPU Assembly Printer
151-
; GCN-O0-NEXT: Free MachineFunction
147+
; GCN-O0-NEXT: CallGraph Construction
148+
; GCN-O0-NEXT: Call Graph SCC Pass Manager
149+
; GCN-O0-NEXT: DummyCGSCCPass
150+
; GCN-O0-NEXT: FunctionPass Manager
151+
; GCN-O0-NEXT: Lazy Machine Block Frequency Analysis
152+
; GCN-O0-NEXT: Machine Optimization Remark Emitter
153+
; GCN-O0-NEXT: AMDGPU Assembly Printer
154+
; GCN-O0-NEXT: Free MachineFunction
152155

153156
; GCN-O1:Target Library Information
154157
; GCN-O1-NEXT:Target Pass Configuration
@@ -420,11 +423,14 @@
420423
; GCN-O1-NEXT: Machine Optimization Remark Emitter
421424
; GCN-O1-NEXT: Stack Frame Layout Analysis
422425
; GCN-O1-NEXT: Function register usage analysis
423-
; GCN-O1-NEXT: FunctionPass Manager
424-
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
425-
; GCN-O1-NEXT: Machine Optimization Remark Emitter
426-
; GCN-O1-NEXT: AMDGPU Assembly Printer
427-
; GCN-O1-NEXT: Free MachineFunction
426+
; GCN-O1-NEXT: CallGraph Construction
427+
; GCN-O1-NEXT: Call Graph SCC Pass Manager
428+
; GCN-O1-NEXT: DummyCGSCCPass
429+
; GCN-O1-NEXT: FunctionPass Manager
430+
; GCN-O1-NEXT: Lazy Machine Block Frequency Analysis
431+
; GCN-O1-NEXT: Machine Optimization Remark Emitter
432+
; GCN-O1-NEXT: AMDGPU Assembly Printer
433+
; GCN-O1-NEXT: Free MachineFunction
428434

429435
; GCN-O1-OPTS:Target Library Information
430436
; GCN-O1-OPTS-NEXT:Target Pass Configuration
@@ -718,11 +724,14 @@
718724
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
719725
; GCN-O1-OPTS-NEXT: Stack Frame Layout Analysis
720726
; GCN-O1-OPTS-NEXT: Function register usage analysis
721-
; GCN-O1-OPTS-NEXT: FunctionPass Manager
722-
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
723-
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
724-
; GCN-O1-OPTS-NEXT: AMDGPU Assembly Printer
725-
; GCN-O1-OPTS-NEXT: Free MachineFunction
727+
; GCN-O1-OPTS-NEXT: CallGraph Construction
728+
; GCN-O1-OPTS-NEXT: Call Graph SCC Pass Manager
729+
; GCN-O1-OPTS-NEXT: DummyCGSCCPass
730+
; GCN-O1-OPTS-NEXT: FunctionPass Manager
731+
; GCN-O1-OPTS-NEXT: Lazy Machine Block Frequency Analysis
732+
; GCN-O1-OPTS-NEXT: Machine Optimization Remark Emitter
733+
; GCN-O1-OPTS-NEXT: AMDGPU Assembly Printer
734+
; GCN-O1-OPTS-NEXT: Free MachineFunction
726735

727736
; GCN-O2:Target Library Information
728737
; GCN-O2-NEXT:Target Pass Configuration
@@ -1026,11 +1035,14 @@
10261035
; GCN-O2-NEXT: Machine Optimization Remark Emitter
10271036
; GCN-O2-NEXT: Stack Frame Layout Analysis
10281037
; GCN-O2-NEXT: Function register usage analysis
1029-
; GCN-O2-NEXT: FunctionPass Manager
1030-
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
1031-
; GCN-O2-NEXT: Machine Optimization Remark Emitter
1032-
; GCN-O2-NEXT: AMDGPU Assembly Printer
1033-
; GCN-O2-NEXT: Free MachineFunction
1038+
; GCN-O2-NEXT: CallGraph Construction
1039+
; GCN-O2-NEXT: Call Graph SCC Pass Manager
1040+
; GCN-O2-NEXT: DummyCGSCCPass
1041+
; GCN-O2-NEXT: FunctionPass Manager
1042+
; GCN-O2-NEXT: Lazy Machine Block Frequency Analysis
1043+
; GCN-O2-NEXT: Machine Optimization Remark Emitter
1044+
; GCN-O2-NEXT: AMDGPU Assembly Printer
1045+
; GCN-O2-NEXT: Free MachineFunction
10341046

10351047
; GCN-O3:Target Library Information
10361048
; GCN-O3-NEXT:Target Pass Configuration
@@ -1346,11 +1358,14 @@
13461358
; GCN-O3-NEXT: Machine Optimization Remark Emitter
13471359
; GCN-O3-NEXT: Stack Frame Layout Analysis
13481360
; GCN-O3-NEXT: Function register usage analysis
1349-
; GCN-O3-NEXT: FunctionPass Manager
1350-
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
1351-
; GCN-O3-NEXT: Machine Optimization Remark Emitter
1352-
; GCN-O3-NEXT: AMDGPU Assembly Printer
1353-
; GCN-O3-NEXT: Free MachineFunction
1361+
; GCN-O3-NEXT: CallGraph Construction
1362+
; GCN-O3-NEXT: Call Graph SCC Pass Manager
1363+
; GCN-O3-NEXT: DummyCGSCCPass
1364+
; GCN-O3-NEXT: FunctionPass Manager
1365+
; GCN-O3-NEXT: Lazy Machine Block Frequency Analysis
1366+
; GCN-O3-NEXT: Machine Optimization Remark Emitter
1367+
; GCN-O3-NEXT: AMDGPU Assembly Printer
1368+
; GCN-O3-NEXT: Free MachineFunction
13541369

13551370
define void @empty() {
13561371
ret void

‎llvm/test/CodeGen/AMDGPU/lower-module-lds-offsets.ll

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,19 @@
99
@lds.size.1.align.1 = internal unnamed_addr addrspace(3) global [1 x i8] undef, align 1
1010
@lds.size.16.align.16 = internal unnamed_addr addrspace(3) global [16 x i8] undef, align 16
1111

12+
; GCN-LABEL: {{^}}f0:
13+
; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
14+
; GCN-DAG: v_mov_b32_e32 [[TREE:v[0-9]+]], 3
15+
; GCN: ds_write_b8 [[NULL]], [[TREE]]
16+
define void @f0() {
17+
; OPT-LABEL: @f0(
18+
; OPT-NEXT: store i8 3, ptr addrspace(3) @llvm.amdgcn.module.lds, align 1
19+
; OPT-NEXT: ret void
20+
;
21+
store i8 3, ptr addrspace(3) @lds.size.1.align.1, align 1
22+
ret void
23+
}
24+
1225
; GCN-LABEL: {{^}}k0:
1326
; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
1427
; GCN-DAG: v_mov_b32_e32 [[ONE:v[0-9]+]], 1
@@ -29,16 +42,3 @@ define amdgpu_kernel void @k0() {
2942
call void @f0()
3043
ret void
3144
}
32-
33-
; GCN-LABEL: {{^}}f0:
34-
; GCN-DAG: v_mov_b32_e32 [[NULL:v[0-9]+]], 0
35-
; GCN-DAG: v_mov_b32_e32 [[TREE:v[0-9]+]], 3
36-
; GCN: ds_write_b8 [[NULL]], [[TREE]]
37-
define void @f0() {
38-
; OPT-LABEL: @f0() {
39-
; OPT-NEXT: store i8 3, ptr addrspace(3) @llvm.amdgcn.module.lds, align 1
40-
; OPT-NEXT: ret void
41-
;
42-
store i8 3, ptr addrspace(3) @lds.size.1.align.1, align 1
43-
ret void
44-
}

‎llvm/test/CodeGen/AMDGPU/module-lds-false-sharing.ll

Lines changed: 51 additions & 49 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,55 @@ store i32 0, ptr addrspace(3) @used_by_kernel
2424
}
2525
; CHECK: ; LDSByteSize: 4 bytes
2626

27+
define void @nonkernel() {
28+
; GFX9-LABEL: nonkernel:
29+
; GFX9: ; %bb.0:
30+
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
31+
; GFX9-NEXT: v_mov_b32_e32 v0, 0
32+
; GFX9-NEXT: v_mov_b32_e32 v1, v0
33+
; GFX9-NEXT: ds_write_b32 v0, v0 offset:8
34+
; GFX9-NEXT: ds_write_b64 v0, v[0:1]
35+
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
36+
; GFX9-NEXT: s_setpc_b64 s[30:31]
37+
;
38+
; GFX10-LABEL: nonkernel:
39+
; GFX10: ; %bb.0:
40+
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
41+
; GFX10-NEXT: v_mov_b32_e32 v0, 0
42+
; GFX10-NEXT: v_mov_b32_e32 v1, v0
43+
; GFX10-NEXT: ds_write_b32 v0, v0 offset:8
44+
; GFX10-NEXT: ds_write_b64 v0, v[0:1]
45+
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
46+
; GFX10-NEXT: s_setpc_b64 s[30:31]
47+
;
48+
; G_GFX9-LABEL: nonkernel:
49+
; G_GFX9: ; %bb.0:
50+
; G_GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
51+
; G_GFX9-NEXT: v_mov_b32_e32 v2, 0
52+
; G_GFX9-NEXT: v_mov_b32_e32 v3, 8
53+
; G_GFX9-NEXT: v_mov_b32_e32 v0, 0
54+
; G_GFX9-NEXT: v_mov_b32_e32 v1, 0
55+
; G_GFX9-NEXT: ds_write_b32 v3, v2
56+
; G_GFX9-NEXT: ds_write_b64 v2, v[0:1]
57+
; G_GFX9-NEXT: s_waitcnt lgkmcnt(0)
58+
; G_GFX9-NEXT: s_setpc_b64 s[30:31]
59+
;
60+
; G_GFX10-LABEL: nonkernel:
61+
; G_GFX10: ; %bb.0:
62+
; G_GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
63+
; G_GFX10-NEXT: v_mov_b32_e32 v2, 0
64+
; G_GFX10-NEXT: v_mov_b32_e32 v3, 8
65+
; G_GFX10-NEXT: v_mov_b32_e32 v0, 0
66+
; G_GFX10-NEXT: v_mov_b32_e32 v1, 0
67+
; G_GFX10-NEXT: ds_write_b32 v3, v2
68+
; G_GFX10-NEXT: ds_write_b64 v2, v[0:1]
69+
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
70+
; G_GFX10-NEXT: s_setpc_b64 s[30:31]
71+
store i32 0, ptr addrspace(3) @used_by_both
72+
store double 0.0, ptr addrspace(3) @used_by_function
73+
ret void
74+
}
75+
2776
; Needs to allocate both variables, store to used_by_both is at sizeof(double)
2877
define amdgpu_kernel void @withcall() {
2978
; GFX9-LABEL: withcall:
@@ -139,52 +188,5 @@ define amdgpu_kernel void @nocall_false_sharing() {
139188
}
140189
; CHECK: ; LDSByteSize: 4 bytes
141190

142-
143-
define void @nonkernel() {
144-
; GFX9-LABEL: nonkernel:
145-
; GFX9: ; %bb.0:
146-
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
147-
; GFX9-NEXT: v_mov_b32_e32 v0, 0
148-
; GFX9-NEXT: v_mov_b32_e32 v1, v0
149-
; GFX9-NEXT: ds_write_b32 v0, v0 offset:8
150-
; GFX9-NEXT: ds_write_b64 v0, v[0:1]
151-
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
152-
; GFX9-NEXT: s_setpc_b64 s[30:31]
153-
;
154-
; GFX10-LABEL: nonkernel:
155-
; GFX10: ; %bb.0:
156-
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
157-
; GFX10-NEXT: v_mov_b32_e32 v0, 0
158-
; GFX10-NEXT: v_mov_b32_e32 v1, v0
159-
; GFX10-NEXT: ds_write_b32 v0, v0 offset:8
160-
; GFX10-NEXT: ds_write_b64 v0, v[0:1]
161-
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
162-
; GFX10-NEXT: s_setpc_b64 s[30:31]
163-
;
164-
; G_GFX9-LABEL: nonkernel:
165-
; G_GFX9: ; %bb.0:
166-
; G_GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
167-
; G_GFX9-NEXT: v_mov_b32_e32 v2, 0
168-
; G_GFX9-NEXT: v_mov_b32_e32 v3, 8
169-
; G_GFX9-NEXT: v_mov_b32_e32 v0, 0
170-
; G_GFX9-NEXT: v_mov_b32_e32 v1, 0
171-
; G_GFX9-NEXT: ds_write_b32 v3, v2
172-
; G_GFX9-NEXT: ds_write_b64 v2, v[0:1]
173-
; G_GFX9-NEXT: s_waitcnt lgkmcnt(0)
174-
; G_GFX9-NEXT: s_setpc_b64 s[30:31]
175-
;
176-
; G_GFX10-LABEL: nonkernel:
177-
; G_GFX10: ; %bb.0:
178-
; G_GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
179-
; G_GFX10-NEXT: v_mov_b32_e32 v2, 0
180-
; G_GFX10-NEXT: v_mov_b32_e32 v3, 8
181-
; G_GFX10-NEXT: v_mov_b32_e32 v0, 0
182-
; G_GFX10-NEXT: v_mov_b32_e32 v1, 0
183-
; G_GFX10-NEXT: ds_write_b32 v3, v2
184-
; G_GFX10-NEXT: ds_write_b64 v2, v[0:1]
185-
; G_GFX10-NEXT: s_waitcnt lgkmcnt(0)
186-
; G_GFX10-NEXT: s_setpc_b64 s[30:31]
187-
store i32 0, ptr addrspace(3) @used_by_both
188-
store double 0.0, ptr addrspace(3) @used_by_function
189-
ret void
190-
}
191+
!llvm.module.flags = !{!0}
192+
!0 = !{i32 1, !"amdgpu_code_object_version", i32 500}

‎llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll

Lines changed: 1 addition & 1 deletion
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@gv.fptr0 = external hidden unnamed_addr addrspace(4) constant ptr, align 4
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9-
; GCN-LABEL: unreachable:
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; GCN-NOT: unreachable:
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; Function info:
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; codeLenInByte = 4
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define internal fastcc void @unreachable() {

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