Skip to content

Commit 539ce7c

Browse files
ronliebronlieb
authored
merge main into amd-staging (llvm#2107)
2 parents 58b9ff6 + cab00da commit 539ce7c

File tree

31 files changed

+520
-356
lines changed

31 files changed

+520
-356
lines changed

‎bolt/lib/Rewrite/BuildIDRewriter.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -78,8 +78,7 @@ Error BuildIDRewriter::sectionInitializer() {
7878
"out of bounds while reading note section: %s",
7979
toString(Cursor.takeError()).c_str());
8080

81-
if (Type == ELF::NT_GNU_BUILD_ID && Name.substr(0, 3) == "GNU" &&
82-
DescSz) {
81+
if (Type == ELF::NT_GNU_BUILD_ID && Name.starts_with("GNU") && DescSz) {
8382
BuildIDSection = NoteSection;
8483
BuildID = Desc;
8584
BC.setFileBuildID(getPrintableBuildID(Desc));

‎clang-tools-extra/clangd/CompileCommands.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -404,8 +404,7 @@ enum DriverMode : unsigned char {
404404
DriverMode getDriverMode(const std::vector<std::string> &Args) {
405405
DriverMode Mode = DM_GCC;
406406
llvm::StringRef Argv0 = Args.front();
407-
if (Argv0.ends_with_insensitive(".exe"))
408-
Argv0 = Argv0.drop_back(strlen(".exe"));
407+
Argv0.consume_back_insensitive(".exe");
409408
if (Argv0.ends_with_insensitive("cl"))
410409
Mode = DM_CL;
411410
for (const llvm::StringRef Arg : Args) {

‎clang/include/clang/Driver/Compilation.h

Lines changed: 2 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -90,14 +90,8 @@ class Compilation {
9090
: TC(TC), BoundArch(BoundArch), DeviceOffloadKind(DeviceOffloadKind) {}
9191

9292
bool operator<(const TCArgsKey &K) const {
93-
if (TC < K.TC)
94-
return true;
95-
else if (TC == K.TC && BoundArch < K.BoundArch)
96-
return true;
97-
else if (TC == K.TC && BoundArch == K.BoundArch &&
98-
DeviceOffloadKind < K.DeviceOffloadKind)
99-
return true;
100-
return false;
93+
return std::tie(TC, BoundArch, DeviceOffloadKind) <
94+
std::tie(K.TC, K.BoundArch, K.DeviceOffloadKind);
10195
}
10296
};
10397
std::map<TCArgsKey, llvm::opt::DerivedArgList *> TCArgs;

‎clang/lib/Driver/Job.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -187,7 +187,7 @@ rewriteIncludes(const llvm::ArrayRef<const char *> &Args, size_t Idx,
187187
StringRef FlagRef(Args[Idx + NumArgs - 1]);
188188
assert((FlagRef.starts_with("-F") || FlagRef.starts_with("-I")) &&
189189
"Expecting -I or -F");
190-
StringRef Inc = FlagRef.slice(2, StringRef::npos);
190+
StringRef Inc = FlagRef.substr(2);
191191
if (getAbsPath(Inc, NewInc)) {
192192
SmallString<128> NewArg(FlagRef.slice(0, 2));
193193
NewArg += NewInc;

‎clang/lib/Driver/ToolChain.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1448,7 +1448,7 @@ std::string ToolChain::detectLibcxxVersion(StringRef IncludePath) const {
14481448
StringRef VersionText = llvm::sys::path::filename(LI->path());
14491449
int Version;
14501450
if (VersionText[0] == 'v' &&
1451-
!VersionText.slice(1, StringRef::npos).getAsInteger(10, Version)) {
1451+
!VersionText.substr(1).getAsInteger(10, Version)) {
14521452
if (Version > MaxVersion) {
14531453
MaxVersion = Version;
14541454
MaxVersionString = std::string(VersionText);

‎clang/lib/Frontend/FrontendAction.cpp

Lines changed: 1 addition & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -100,11 +100,7 @@ class DeserializedDeclsSourceRangePrinter : public ASTConsumer,
100100
unsigned Column;
101101

102102
bool operator<(const Position &other) const {
103-
if (Line < other.Line)
104-
return true;
105-
if (Line > other.Line)
106-
return false;
107-
return Column < other.Column;
103+
return std::tie(Line, Column) < std::tie(other.Line, other.Column);
108104
}
109105

110106
static Position GetBeginSpelling(const SourceManager &SM,

‎clang/lib/StaticAnalyzer/Checkers/TestAfterDivZeroChecker.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -41,11 +41,8 @@ class ZeroState {
4141
}
4242

4343
bool operator<(const ZeroState &X) const {
44-
if (BlockID != X.BlockID)
45-
return BlockID < X.BlockID;
46-
if (SFC != X.SFC)
47-
return SFC < X.SFC;
48-
return ZeroSymbol < X.ZeroSymbol;
44+
return std::tie(BlockID, SFC, ZeroSymbol) <
45+
std::tie(X.BlockID, X.SFC, X.ZeroSymbol);
4946
}
5047

5148
void Profile(llvm::FoldingSetNodeID &ID) const {

‎clang/utils/TableGen/ClangOptionDocEmitter.cpp

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -205,10 +205,7 @@ std::string escapeRST(StringRef Str) {
205205
}
206206

207207
StringRef getSphinxOptionID(StringRef OptionName) {
208-
for (auto I = OptionName.begin(), E = OptionName.end(); I != E; ++I)
209-
if (!isalnum(*I) && *I != '-')
210-
return OptionName.substr(0, I - OptionName.begin());
211-
return OptionName;
208+
return OptionName.take_while([](char C) { return isalnum(C) || C == '-'; });
212209
}
213210

214211
bool canSphinxCopeWithOption(const Record *Option) {

‎llvm/include/llvm/Support/InstructionCost.h

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@
2020

2121
#include "llvm/Support/MathExtras.h"
2222
#include <limits>
23+
#include <tuple>
2324

2425
namespace llvm {
2526

@@ -191,9 +192,7 @@ class InstructionCost {
191192
/// the states are valid and users can test for validity of the cost
192193
/// explicitly.
193194
bool operator<(const InstructionCost &RHS) const {
194-
if (State != RHS.State)
195-
return State < RHS.State;
196-
return Value < RHS.Value;
195+
return std::tie(State, Value) < std::tie(RHS.State, RHS.Value);
197196
}
198197

199198
bool operator==(const InstructionCost &RHS) const {

‎llvm/lib/Analysis/ScalarEvolution.cpp

Lines changed: 28 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -15867,49 +15867,45 @@ const SCEV *ScalarEvolution::LoopGuards::rewrite(const SCEV *Expr) const {
1586715867
}
1586815868

1586915869
const SCEV *visitZeroExtendExpr(const SCEVZeroExtendExpr *Expr) {
15870-
auto I = Map.find(Expr);
15871-
if (I == Map.end()) {
15872-
// If we didn't find the extact ZExt expr in the map, check if there's
15873-
// an entry for a smaller ZExt we can use instead.
15874-
Type *Ty = Expr->getType();
15875-
const SCEV *Op = Expr->getOperand(0);
15876-
unsigned Bitwidth = Ty->getScalarSizeInBits() / 2;
15877-
while (Bitwidth % 8 == 0 && Bitwidth >= 8 &&
15878-
Bitwidth > Op->getType()->getScalarSizeInBits()) {
15879-
Type *NarrowTy = IntegerType::get(SE.getContext(), Bitwidth);
15880-
auto *NarrowExt = SE.getZeroExtendExpr(Op, NarrowTy);
15881-
auto I = Map.find(NarrowExt);
15882-
if (I != Map.end())
15883-
return SE.getZeroExtendExpr(I->second, Ty);
15884-
Bitwidth = Bitwidth / 2;
15885-
}
15870+
if (const SCEV *S = Map.lookup(Expr))
15871+
return S;
1588615872

15887-
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitZeroExtendExpr(
15888-
Expr);
15873+
// If we didn't find the extact ZExt expr in the map, check if there's
15874+
// an entry for a smaller ZExt we can use instead.
15875+
Type *Ty = Expr->getType();
15876+
const SCEV *Op = Expr->getOperand(0);
15877+
unsigned Bitwidth = Ty->getScalarSizeInBits() / 2;
15878+
while (Bitwidth % 8 == 0 && Bitwidth >= 8 &&
15879+
Bitwidth > Op->getType()->getScalarSizeInBits()) {
15880+
Type *NarrowTy = IntegerType::get(SE.getContext(), Bitwidth);
15881+
auto *NarrowExt = SE.getZeroExtendExpr(Op, NarrowTy);
15882+
auto I = Map.find(NarrowExt);
15883+
if (I != Map.end())
15884+
return SE.getZeroExtendExpr(I->second, Ty);
15885+
Bitwidth = Bitwidth / 2;
1588915886
}
15890-
return I->second;
15887+
15888+
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitZeroExtendExpr(
15889+
Expr);
1589115890
}
1589215891

1589315892
const SCEV *visitSignExtendExpr(const SCEVSignExtendExpr *Expr) {
15894-
auto I = Map.find(Expr);
15895-
if (I == Map.end())
15896-
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitSignExtendExpr(
15897-
Expr);
15898-
return I->second;
15893+
if (const SCEV *S = Map.lookup(Expr))
15894+
return S;
15895+
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitSignExtendExpr(
15896+
Expr);
1589915897
}
1590015898

1590115899
const SCEV *visitUMinExpr(const SCEVUMinExpr *Expr) {
15902-
auto I = Map.find(Expr);
15903-
if (I == Map.end())
15904-
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitUMinExpr(Expr);
15905-
return I->second;
15900+
if (const SCEV *S = Map.lookup(Expr))
15901+
return S;
15902+
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitUMinExpr(Expr);
1590615903
}
1590715904

1590815905
const SCEV *visitSMinExpr(const SCEVSMinExpr *Expr) {
15909-
auto I = Map.find(Expr);
15910-
if (I == Map.end())
15911-
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitSMinExpr(Expr);
15912-
return I->second;
15906+
if (const SCEV *S = Map.lookup(Expr))
15907+
return S;
15908+
return SCEVRewriteVisitor<SCEVLoopGuardRewriter>::visitSMinExpr(Expr);
1591315909
}
1591415910

1591515911
const SCEV *visitAddExpr(const SCEVAddExpr *Expr) {

‎llvm/lib/Bitcode/Writer/BitcodeWriter.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2774,9 +2774,9 @@ void ModuleBitcodeWriter::writeFunctionMetadataAttachment(const Function &F) {
27742774

27752775
Record.push_back(VE.getInstructionID(&I));
27762776

2777-
for (unsigned i = 0, e = MDs.size(); i != e; ++i) {
2778-
Record.push_back(MDs[i].first);
2779-
Record.push_back(VE.getMetadataID(MDs[i].second));
2777+
for (const auto &[ID, MD] : MDs) {
2778+
Record.push_back(ID);
2779+
Record.push_back(VE.getMetadataID(MD));
27802780
}
27812781
Stream.EmitRecord(bitc::METADATA_ATTACHMENT, Record, 0);
27822782
Record.clear();

‎llvm/lib/Bitcode/Writer/ValueEnumerator.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -485,8 +485,8 @@ ValueEnumerator::ValueEnumerator(const Module &M,
485485
// Enumerate metadata attached with this instruction.
486486
MDs.clear();
487487
I.getAllMetadataOtherThanDebugLoc(MDs);
488-
for (unsigned i = 0, e = MDs.size(); i != e; ++i)
489-
EnumerateMetadata(&F, MDs[i].second);
488+
for (const auto &MD : MDs)
489+
EnumerateMetadata(&F, MD.second);
490490

491491
// Don't enumerate the location directly -- it has a special record
492492
// type -- but enumerate its operands.

‎llvm/lib/Support/APFloat.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -3262,9 +3262,8 @@ bool IEEEFloat::convertFromStringSpecials(StringRef str) {
32623262
return true;
32633263
}
32643264

3265-
bool IsNegative = str.front() == '-';
3265+
bool IsNegative = str.consume_front("-");
32663266
if (IsNegative) {
3267-
str = str.drop_front();
32683267
if (str.size() < MIN_NAME_SIZE)
32693268
return false;
32703269

@@ -3275,16 +3274,13 @@ bool IEEEFloat::convertFromStringSpecials(StringRef str) {
32753274
}
32763275

32773276
// If we have a 's' (or 'S') prefix, then this is a Signaling NaN.
3278-
bool IsSignaling = str.front() == 's' || str.front() == 'S';
3277+
bool IsSignaling = str.consume_front_insensitive("s");
32793278
if (IsSignaling) {
3280-
str = str.drop_front();
32813279
if (str.size() < MIN_NAME_SIZE)
32823280
return false;
32833281
}
32843282

3285-
if (str.starts_with("nan") || str.starts_with("NaN")) {
3286-
str = str.drop_front(3);
3287-
3283+
if (str.consume_front("nan") || str.consume_front("NaN")) {
32883284
// A NaN without payload.
32893285
if (str.empty()) {
32903286
makeNaN(IsSignaling, IsNegative);

‎llvm/lib/Target/AVR/AVRISelLowering.cpp

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -220,40 +220,6 @@ AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
220220
setMinimumJumpTableEntries(UINT_MAX);
221221
}
222222

223-
const char *AVRTargetLowering::getTargetNodeName(unsigned Opcode) const {
224-
#define NODE(name) \
225-
case AVRISD::name: \
226-
return #name
227-
228-
switch (Opcode) {
229-
default:
230-
return nullptr;
231-
NODE(RET_GLUE);
232-
NODE(RETI_GLUE);
233-
NODE(CALL);
234-
NODE(WRAPPER);
235-
NODE(LSL);
236-
NODE(LSLW);
237-
NODE(LSR);
238-
NODE(LSRW);
239-
NODE(ROL);
240-
NODE(ROR);
241-
NODE(ASR);
242-
NODE(ASRW);
243-
NODE(LSLLOOP);
244-
NODE(LSRLOOP);
245-
NODE(ROLLOOP);
246-
NODE(RORLOOP);
247-
NODE(ASRLOOP);
248-
NODE(BRCOND);
249-
NODE(CMP);
250-
NODE(CMPC);
251-
NODE(TST);
252-
NODE(SELECT_CC);
253-
#undef NODE
254-
}
255-
}
256-
257223
EVT AVRTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &,
258224
EVT VT) const {
259225
assert(!VT.isVector() && "No AVR SetCC type for vectors!");

‎llvm/lib/Target/AVR/AVRISelLowering.h

Lines changed: 0 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -19,64 +19,6 @@
1919

2020
namespace llvm {
2121

22-
namespace AVRISD {
23-
24-
/// AVR Specific DAG Nodes
25-
enum NodeType {
26-
/// Start the numbering where the builtin ops leave off.
27-
FIRST_NUMBER = ISD::BUILTIN_OP_END,
28-
/// Return from subroutine.
29-
RET_GLUE,
30-
/// Return from ISR.
31-
RETI_GLUE,
32-
/// Represents an abstract call instruction,
33-
/// which includes a bunch of information.
34-
CALL,
35-
/// A wrapper node for TargetConstantPool,
36-
/// TargetExternalSymbol, and TargetGlobalAddress.
37-
WRAPPER,
38-
LSL, ///< Logical shift left.
39-
LSLBN, ///< Byte logical shift left N bits.
40-
LSLWN, ///< Word logical shift left N bits.
41-
LSLHI, ///< Higher 8-bit of word logical shift left.
42-
LSLW, ///< Wide logical shift left.
43-
LSR, ///< Logical shift right.
44-
LSRBN, ///< Byte logical shift right N bits.
45-
LSRWN, ///< Word logical shift right N bits.
46-
LSRLO, ///< Lower 8-bit of word logical shift right.
47-
LSRW, ///< Wide logical shift right.
48-
ASR, ///< Arithmetic shift right.
49-
ASRBN, ///< Byte arithmetic shift right N bits.
50-
ASRWN, ///< Word arithmetic shift right N bits.
51-
ASRLO, ///< Lower 8-bit of word arithmetic shift right.
52-
ASRW, ///< Wide arithmetic shift right.
53-
ROR, ///< Bit rotate right.
54-
ROL, ///< Bit rotate left.
55-
LSLLOOP, ///< A loop of single logical shift left instructions.
56-
LSRLOOP, ///< A loop of single logical shift right instructions.
57-
ROLLOOP, ///< A loop of single left bit rotate instructions.
58-
RORLOOP, ///< A loop of single right bit rotate instructions.
59-
ASRLOOP, ///< A loop of single arithmetic shift right instructions.
60-
/// AVR conditional branches. Operand 0 is the chain operand, operand 1
61-
/// is the block to branch if condition is true, operand 2 is the
62-
/// condition code, and operand 3 is the flag operand produced by a CMP
63-
/// or TEST instruction.
64-
BRCOND,
65-
/// Compare instruction.
66-
CMP,
67-
/// Compare with carry instruction.
68-
CMPC,
69-
/// Test for zero or minus instruction.
70-
TST,
71-
/// Swap Rd[7:4] <-> Rd[3:0].
72-
SWAP,
73-
/// Operand 0 and operand 1 are selection variable, operand 2
74-
/// is condition code and operand 3 is flag operand.
75-
SELECT_CC
76-
};
77-
78-
} // end of namespace AVRISD
79-
8022
class AVRSubtarget;
8123
class AVRTargetMachine;
8224

@@ -95,8 +37,6 @@ class AVRTargetLowering : public TargetLowering {
9537
return MVT::i8;
9638
}
9739

98-
const char *getTargetNodeName(unsigned Opcode) const override;
99-
10040
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
10141

10242
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,

0 commit comments

Comments
 (0)