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[AMDGPU] Merge the conditions used for deciding CS spills for amdgpu_cs_chain[_preserve] (llvm#109911)
Multiple conditions exist to decide whether callee save spills/restores are required for amdgpu_cs_chain or amdgpu_cs_chain_preserve calling conventions. This patch consolidates them all and moves to a single place. Change-Id: Iceb4609d0b9505ea3ec09023887d4e9261d8d033
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-12
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2 files changed

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-12
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llvm/lib/Target/AMDGPU/SIFrameLowering.cpp

Lines changed: 4 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1601,16 +1601,10 @@ void SIFrameLowering::processFunctionBeforeFrameFinalized(
16011601
SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
16021602

16031603
// Allocate spill slots for WWM reserved VGPRs.
1604-
// For chain functions, we only need to do this if we have calls to
1605-
// llvm.amdgcn.cs.chain.
1606-
bool IsChainWithoutCalls =
1607-
FuncInfo->isChainFunction() && !MF.getFrameInfo().hasTailCall();
1608-
if (!FuncInfo->isEntryFunction() && !IsChainWithoutCalls) {
1609-
for (Register Reg : FuncInfo->getWWMReservedRegs()) {
1610-
const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
1611-
FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC),
1612-
TRI->getSpillAlign(*RC));
1613-
}
1604+
for (Register Reg : FuncInfo->getWWMReservedRegs()) {
1605+
const TargetRegisterClass *RC = TRI->getPhysRegBaseClass(Reg);
1606+
FuncInfo->allocateWWMSpill(MF, Reg, TRI->getSpillSize(*RC),
1607+
TRI->getSpillAlign(*RC));
16141608
}
16151609

16161610
const bool SpillVGPRToAGPR = ST.hasMAIInsts() && FuncInfo->hasSpilledVGPRs()

llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -280,8 +280,10 @@ void SIMachineFunctionInfo::allocateWWMSpill(MachineFunction &MF, Register VGPR,
280280
// amdgpu_cs_chain_preserve calling convention and this is a scratch register.
281281
// We never need to allocate a spill for these because we don't even need to
282282
// restore the inactive lanes for them (they're scratchier than the usual
283-
// scratch registers).
284-
if (isChainFunction() && SIRegisterInfo::isChainScratchRegister(VGPR))
283+
// scratch registers). We only need to do this if we have calls to
284+
// llvm.amdgcn.cs.chain.
285+
if (isChainFunction() && (SIRegisterInfo::isChainScratchRegister(VGPR) ||
286+
!MF.getFrameInfo().hasTailCall()))
285287
return;
286288

287289
WWMSpills.insert(std::make_pair(

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