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woruyuRKSimon
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ronlieb
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[DAG] Refactor X86 combineVSelectWithAllOnesOrZeros fold into a generic DAG Combine (llvm#145298)
This PR resolves llvm#144513 The modification include five pattern : 1.vselect Cond, 0, 0 → 0 2.vselect Cond, -1, 0 → bitcast Cond 3.vselect Cond, -1, x → or Cond, x 4.vselect Cond, x, 0 → and Cond, x 5.vselect Cond, 000..., X -> andn Cond, X 1-4 have been migrated to DAGCombine. 5 still in x86 code. The reason is that you cannot use the andn instruction directly in DAGCombine, you can only use and+xor, which will introduce optimization order issues. For example, in the x86 backend, select Cond, 0, x → (~Cond) & x, the backend will first check whether the cond node of (~Cond) is a setcc node. If so, it will modify the comparison operator of the condition.So the x86 backend cannot complete the optimization of andn.In short, I think it is a better choice to keep the pattern of vselect Cond, 000..., X instead of and+xor in combineDAG. For commit, the first is code changes and x86 test(note 1), the second is tests in other backend(node 2). --------- Co-authored-by: Simon Pilgrim <[email protected]>
1 parent 358348b commit 5a3d107

20 files changed

+247
-247
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 96 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13069,6 +13069,99 @@ SDValue DAGCombiner::visitVP_SELECT(SDNode *N) {
1306913069
return SDValue();
1307013070
}
1307113071

13072+
static SDValue combineVSelectWithAllOnesOrZeros(SDValue Cond, SDValue TVal,
13073+
SDValue FVal,
13074+
const TargetLowering &TLI,
13075+
SelectionDAG &DAG,
13076+
const SDLoc &DL) {
13077+
if (!TLI.isTypeLegal(TVal.getValueType()))
13078+
return SDValue();
13079+
13080+
EVT VT = TVal.getValueType();
13081+
EVT CondVT = Cond.getValueType();
13082+
13083+
assert(CondVT.isVector() && "Vector select expects a vector selector!");
13084+
13085+
bool IsTAllZero = ISD::isBuildVectorAllZeros(TVal.getNode());
13086+
bool IsTAllOne = ISD::isBuildVectorAllOnes(TVal.getNode());
13087+
bool IsFAllZero = ISD::isBuildVectorAllZeros(FVal.getNode());
13088+
bool IsFAllOne = ISD::isBuildVectorAllOnes(FVal.getNode());
13089+
13090+
// no vselect(cond, 0/-1, X) or vselect(cond, X, 0/-1), return
13091+
if (!IsTAllZero && !IsTAllOne && !IsFAllZero && !IsFAllOne)
13092+
return SDValue();
13093+
13094+
// select Cond, 0, 0 → 0
13095+
if (IsTAllZero && IsFAllZero) {
13096+
return VT.isFloatingPoint() ? DAG.getConstantFP(0.0, DL, VT)
13097+
: DAG.getConstant(0, DL, VT);
13098+
}
13099+
13100+
// check select(setgt lhs, -1), 1, -1 --> or (sra lhs, bitwidth - 1), 1
13101+
APInt TValAPInt;
13102+
if (Cond.getOpcode() == ISD::SETCC &&
13103+
Cond.getOperand(2) == DAG.getCondCode(ISD::SETGT) &&
13104+
Cond.getOperand(0).getValueType() == VT && VT.isSimple() &&
13105+
ISD::isConstantSplatVector(TVal.getNode(), TValAPInt) &&
13106+
TValAPInt.isOne() &&
13107+
ISD::isConstantSplatVectorAllOnes(Cond.getOperand(1).getNode()) &&
13108+
ISD::isConstantSplatVectorAllOnes(FVal.getNode())) {
13109+
return SDValue();
13110+
}
13111+
13112+
// To use the condition operand as a bitwise mask, it must have elements that
13113+
// are the same size as the select elements. Ie, the condition operand must
13114+
// have already been promoted from the IR select condition type <N x i1>.
13115+
// Don't check if the types themselves are equal because that excludes
13116+
// vector floating-point selects.
13117+
if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
13118+
return SDValue();
13119+
13120+
// Cond value must be 'sign splat' to be converted to a logical op.
13121+
if (DAG.ComputeNumSignBits(Cond) != CondVT.getScalarSizeInBits())
13122+
return SDValue();
13123+
13124+
// Try inverting Cond and swapping T/F if it gives all-ones/all-zeros form
13125+
if (!IsTAllOne && !IsFAllZero && Cond.hasOneUse() &&
13126+
Cond.getOpcode() == ISD::SETCC &&
13127+
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
13128+
CondVT) {
13129+
if (IsTAllZero || IsFAllOne) {
13130+
SDValue CC = Cond.getOperand(2);
13131+
ISD::CondCode InverseCC = ISD::getSetCCInverse(
13132+
cast<CondCodeSDNode>(CC)->get(), Cond.getOperand(0).getValueType());
13133+
Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1),
13134+
InverseCC);
13135+
std::swap(TVal, FVal);
13136+
std::swap(IsTAllOne, IsFAllOne);
13137+
std::swap(IsTAllZero, IsFAllZero);
13138+
}
13139+
}
13140+
13141+
assert(DAG.ComputeNumSignBits(Cond) == CondVT.getScalarSizeInBits() &&
13142+
"Select condition no longer all-sign bits");
13143+
13144+
// select Cond, -1, 0 → bitcast Cond
13145+
if (IsTAllOne && IsFAllZero)
13146+
return DAG.getBitcast(VT, Cond);
13147+
13148+
// select Cond, -1, x → or Cond, x
13149+
if (IsTAllOne) {
13150+
SDValue X = DAG.getBitcast(CondVT, FVal);
13151+
SDValue Or = DAG.getNode(ISD::OR, DL, CondVT, Cond, X);
13152+
return DAG.getBitcast(VT, Or);
13153+
}
13154+
13155+
// select Cond, x, 0 → and Cond, x
13156+
if (IsFAllZero) {
13157+
SDValue X = DAG.getBitcast(CondVT, TVal);
13158+
SDValue And = DAG.getNode(ISD::AND, DL, CondVT, Cond, X);
13159+
return DAG.getBitcast(VT, And);
13160+
}
13161+
13162+
return SDValue();
13163+
}
13164+
1307213165
SDValue DAGCombiner::visitVSELECT(SDNode *N) {
1307313166
SDValue N0 = N->getOperand(0);
1307413167
SDValue N1 = N->getOperand(1);
@@ -13337,6 +13430,9 @@ SDValue DAGCombiner::visitVSELECT(SDNode *N) {
1333713430
if (SimplifyDemandedVectorElts(SDValue(N, 0)))
1333813431
return SDValue(N, 0);
1333913432

13433+
if (SDValue V = combineVSelectWithAllOnesOrZeros(N0, N1, N2, TLI, DAG, DL))
13434+
return V;
13435+
1334013436
return SDValue();
1334113437
}
1334213438

‎llvm/lib/Target/X86/X86ISelLowering.cpp

Lines changed: 9 additions & 63 deletions
Original file line numberDiff line numberDiff line change
@@ -47255,13 +47255,14 @@ static SDValue combineToExtendBoolVectorInReg(
4725547255
DAG.getConstant(EltSizeInBits - 1, DL, VT));
4725647256
}
4725747257

47258-
/// If a vector select has an operand that is -1 or 0, try to simplify the
47258+
/// If a vector select has an left operand that is 0, try to simplify the
4725947259
/// select to a bitwise logic operation.
47260-
/// TODO: Move to DAGCombiner, possibly using TargetLowering::hasAndNot()?
47261-
static SDValue
47262-
combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
47263-
TargetLowering::DAGCombinerInfo &DCI,
47264-
const X86Subtarget &Subtarget) {
47260+
/// TODO: Move to DAGCombiner.combineVSelectWithAllOnesOrZeros, possibly using
47261+
/// TargetLowering::hasAndNot()?
47262+
static SDValue combineVSelectWithLastZeros(SDNode *N, SelectionDAG &DAG,
47263+
const SDLoc &DL,
47264+
TargetLowering::DAGCombinerInfo &DCI,
47265+
const X86Subtarget &Subtarget) {
4726547266
SDValue Cond = N->getOperand(0);
4726647267
SDValue LHS = N->getOperand(1);
4726747268
SDValue RHS = N->getOperand(2);
@@ -47274,20 +47275,6 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
4727447275

4727547276
assert(CondVT.isVector() && "Vector select expects a vector selector!");
4727647277

47277-
// TODO: Use isNullOrNullSplat() to distinguish constants with undefs?
47278-
// TODO: Can we assert that both operands are not zeros (because that should
47279-
// get simplified at node creation time)?
47280-
bool TValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
47281-
bool FValIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode());
47282-
47283-
// If both inputs are 0/undef, create a complete zero vector.
47284-
// FIXME: As noted above this should be handled by DAGCombiner/getNode.
47285-
if (TValIsAllZeros && FValIsAllZeros) {
47286-
if (VT.isFloatingPoint())
47287-
return DAG.getConstantFP(0.0, DL, VT);
47288-
return DAG.getConstant(0, DL, VT);
47289-
}
47290-
4729147278
// To use the condition operand as a bitwise mask, it must have elements that
4729247279
// are the same size as the select elements. Ie, the condition operand must
4729347280
// have already been promoted from the IR select condition type <N x i1>.
@@ -47296,56 +47283,15 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
4729647283
if (CondVT.getScalarSizeInBits() != VT.getScalarSizeInBits())
4729747284
return SDValue();
4729847285

47299-
// Try to invert the condition if true value is not all 1s and false value is
47300-
// not all 0s. Only do this if the condition has one use.
47301-
bool TValIsAllOnes = ISD::isBuildVectorAllOnes(LHS.getNode());
47302-
if (!TValIsAllOnes && !FValIsAllZeros && Cond.hasOneUse() &&
47303-
// Check if the selector will be produced by CMPP*/PCMP*.
47304-
Cond.getOpcode() == ISD::SETCC &&
47305-
// Check if SETCC has already been promoted.
47306-
TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT) ==
47307-
CondVT) {
47308-
bool FValIsAllOnes = ISD::isBuildVectorAllOnes(RHS.getNode());
47309-
47310-
if (TValIsAllZeros || FValIsAllOnes) {
47311-
SDValue CC = Cond.getOperand(2);
47312-
ISD::CondCode NewCC = ISD::getSetCCInverse(
47313-
cast<CondCodeSDNode>(CC)->get(), Cond.getOperand(0).getValueType());
47314-
Cond = DAG.getSetCC(DL, CondVT, Cond.getOperand(0), Cond.getOperand(1),
47315-
NewCC);
47316-
std::swap(LHS, RHS);
47317-
TValIsAllOnes = FValIsAllOnes;
47318-
FValIsAllZeros = TValIsAllZeros;
47319-
}
47320-
}
47321-
4732247286
// Cond value must be 'sign splat' to be converted to a logical op.
4732347287
if (DAG.ComputeNumSignBits(Cond) != CondVT.getScalarSizeInBits())
4732447288
return SDValue();
4732547289

47326-
// vselect Cond, 111..., 000... -> Cond
47327-
if (TValIsAllOnes && FValIsAllZeros)
47328-
return DAG.getBitcast(VT, Cond);
47329-
4733047290
if (!TLI.isTypeLegal(CondVT))
4733147291
return SDValue();
4733247292

47333-
// vselect Cond, 111..., X -> or Cond, X
47334-
if (TValIsAllOnes) {
47335-
SDValue CastRHS = DAG.getBitcast(CondVT, RHS);
47336-
SDValue Or = DAG.getNode(ISD::OR, DL, CondVT, Cond, CastRHS);
47337-
return DAG.getBitcast(VT, Or);
47338-
}
47339-
47340-
// vselect Cond, X, 000... -> and Cond, X
47341-
if (FValIsAllZeros) {
47342-
SDValue CastLHS = DAG.getBitcast(CondVT, LHS);
47343-
SDValue And = DAG.getNode(ISD::AND, DL, CondVT, Cond, CastLHS);
47344-
return DAG.getBitcast(VT, And);
47345-
}
47346-
4734747293
// vselect Cond, 000..., X -> andn Cond, X
47348-
if (TValIsAllZeros) {
47294+
if (ISD::isBuildVectorAllZeros(LHS.getNode())) {
4734947295
SDValue CastRHS = DAG.getBitcast(CondVT, RHS);
4735047296
SDValue AndN;
4735147297
// The canonical form differs for i1 vectors - x86andnp is not used
@@ -48106,7 +48052,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
4810648052
if (!TLI.isTypeLegal(VT) || isSoftF16(VT, Subtarget))
4810748053
return SDValue();
4810848054

48109-
if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DL, DCI, Subtarget))
48055+
if (SDValue V = combineVSelectWithLastZeros(N, DAG, DL, DCI, Subtarget))
4811048056
return V;
4811148057

4811248058
if (SDValue V = combineVSelectToBLENDV(N, DAG, DL, DCI, Subtarget))

‎llvm/test/CodeGen/AArch64/arm64-zip.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -413,7 +413,7 @@ define <4 x float> @shuffle_zip1(<4 x float> %arg) {
413413
; CHECK-NEXT: fmov.4s v1, #1.00000000
414414
; CHECK-NEXT: zip1.4h v0, v0, v0
415415
; CHECK-NEXT: sshll.4s v0, v0, #0
416-
; CHECK-NEXT: and.16b v0, v1, v0
416+
; CHECK-NEXT: and.16b v0, v0, v1
417417
; CHECK-NEXT: ret
418418
bb:
419419
%inst = fcmp olt <4 x float> zeroinitializer, %arg

‎llvm/test/CodeGen/AArch64/cmp-select-sign.ll

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -197,11 +197,9 @@ define <4 x i32> @not_sign_4xi32(<4 x i32> %a) {
197197
; CHECK-LABEL: not_sign_4xi32:
198198
; CHECK: // %bb.0:
199199
; CHECK-NEXT: adrp x8, .LCPI16_0
200-
; CHECK-NEXT: movi v2.4s, #1
201200
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]
202-
; CHECK-NEXT: cmgt v0.4s, v0.4s, v1.4s
203-
; CHECK-NEXT: and v1.16b, v0.16b, v2.16b
204-
; CHECK-NEXT: orn v0.16b, v1.16b, v0.16b
201+
; CHECK-NEXT: cmge v0.4s, v1.4s, v0.4s
202+
; CHECK-NEXT: orr v0.4s, #1
205203
; CHECK-NEXT: ret
206204
%c = icmp sgt <4 x i32> %a, <i32 1, i32 -1, i32 -1, i32 -1>
207205
%res = select <4 x i1> %c, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>

‎llvm/test/CodeGen/AArch64/concatbinop.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -179,7 +179,7 @@ define <16 x i8> @signOf_neon(ptr nocapture noundef readonly %a, ptr nocapture n
179179
; CHECK-NEXT: uzp1 v3.16b, v5.16b, v6.16b
180180
; CHECK-NEXT: uzp1 v1.16b, v1.16b, v2.16b
181181
; CHECK-NEXT: and v0.16b, v3.16b, v0.16b
182-
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
182+
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
183183
; CHECK-NEXT: ret
184184
entry:
185185
%0 = load <8 x i16>, ptr %a, align 2

‎llvm/test/CodeGen/AArch64/sat-add.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -530,7 +530,7 @@ define <16 x i8> @unsigned_sat_variable_v16i8_using_cmp_notval(<16 x i8> %x, <16
530530
; CHECK-NEXT: mvn v2.16b, v1.16b
531531
; CHECK-NEXT: add v1.16b, v0.16b, v1.16b
532532
; CHECK-NEXT: cmhi v0.16b, v0.16b, v2.16b
533-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
533+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
534534
; CHECK-NEXT: ret
535535
%noty = xor <16 x i8> %y, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
536536
%a = add <16 x i8> %x, %y
@@ -570,7 +570,7 @@ define <8 x i16> @unsigned_sat_variable_v8i16_using_cmp_notval(<8 x i16> %x, <8
570570
; CHECK-NEXT: mvn v2.16b, v1.16b
571571
; CHECK-NEXT: add v1.8h, v0.8h, v1.8h
572572
; CHECK-NEXT: cmhi v0.8h, v0.8h, v2.8h
573-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
573+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
574574
; CHECK-NEXT: ret
575575
%noty = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
576576
%a = add <8 x i16> %x, %y
@@ -610,7 +610,7 @@ define <4 x i32> @unsigned_sat_variable_v4i32_using_cmp_notval(<4 x i32> %x, <4
610610
; CHECK-NEXT: mvn v2.16b, v1.16b
611611
; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
612612
; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
613-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
613+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
614614
; CHECK-NEXT: ret
615615
%noty = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1>
616616
%a = add <4 x i32> %x, %y
@@ -651,7 +651,7 @@ define <2 x i64> @unsigned_sat_variable_v2i64_using_cmp_notval(<2 x i64> %x, <2
651651
; CHECK-NEXT: mvn v2.16b, v1.16b
652652
; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
653653
; CHECK-NEXT: cmhi v0.2d, v0.2d, v2.2d
654-
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
654+
; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b
655655
; CHECK-NEXT: ret
656656
%noty = xor <2 x i64> %y, <i64 -1, i64 -1>
657657
%a = add <2 x i64> %x, %y

‎llvm/test/CodeGen/AArch64/select_cc.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,7 +88,7 @@ define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {
8888
; CHECK-SD-NEXT: ldr d1, [x0]
8989
; CHECK-SD-NEXT: fcmgt v1.2s, v1.2s, #0.0
9090
; CHECK-SD-NEXT: sshll v1.2d, v1.2s, #0
91-
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
91+
; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b
9292
; CHECK-SD-NEXT: ret
9393
;
9494
; CHECK-GI-LABEL: select_olt_load_cmp:

‎llvm/test/CodeGen/AArch64/selectcc-to-shiftand.ll

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -249,9 +249,6 @@ define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {
249249
; CHECK-SD-LABEL: sel_shift_bool_v16i8:
250250
; CHECK-SD: // %bb.0:
251251
; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7
252-
; CHECK-SD-NEXT: movi v1.16b, #128
253-
; CHECK-SD-NEXT: cmlt v0.16b, v0.16b, #0
254-
; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
255252
; CHECK-SD-NEXT: ret
256253
;
257254
; CHECK-GI-LABEL: sel_shift_bool_v16i8:

‎llvm/test/CodeGen/AArch64/tbl-loops.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -31,12 +31,12 @@ define void @loop1(ptr noalias nocapture noundef writeonly %dst, ptr nocapture n
3131
; CHECK-NEXT: add x13, x13, #32
3232
; CHECK-NEXT: fcmgt v3.4s, v1.4s, v0.4s
3333
; CHECK-NEXT: fcmgt v4.4s, v2.4s, v0.4s
34-
; CHECK-NEXT: fcmlt v5.4s, v1.4s, #0.0
35-
; CHECK-NEXT: fcmlt v6.4s, v2.4s, #0.0
36-
; CHECK-NEXT: bit v1.16b, v0.16b, v3.16b
37-
; CHECK-NEXT: bit v2.16b, v0.16b, v4.16b
38-
; CHECK-NEXT: bic v1.16b, v1.16b, v5.16b
39-
; CHECK-NEXT: bic v2.16b, v2.16b, v6.16b
34+
; CHECK-NEXT: bsl v3.16b, v0.16b, v1.16b
35+
; CHECK-NEXT: bsl v4.16b, v0.16b, v2.16b
36+
; CHECK-NEXT: fcmlt v1.4s, v1.4s, #0.0
37+
; CHECK-NEXT: fcmlt v2.4s, v2.4s, #0.0
38+
; CHECK-NEXT: bic v1.16b, v3.16b, v1.16b
39+
; CHECK-NEXT: bic v2.16b, v4.16b, v2.16b
4040
; CHECK-NEXT: fcvtzs v1.4s, v1.4s
4141
; CHECK-NEXT: fcvtzs v2.4s, v2.4s
4242
; CHECK-NEXT: xtn v1.4h, v1.4s

‎llvm/test/CodeGen/AArch64/vselect-constants.ll

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -146,10 +146,8 @@ define <4 x i32> @cmp_sel_0_or_minus1_vec(<4 x i32> %x, <4 x i32> %y) {
146146
define <4 x i32> @sel_1_or_0_vec(<4 x i1> %cond) {
147147
; CHECK-LABEL: sel_1_or_0_vec:
148148
; CHECK: // %bb.0:
149-
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
150149
; CHECK-NEXT: movi v1.4s, #1
151-
; CHECK-NEXT: shl v0.4s, v0.4s, #31
152-
; CHECK-NEXT: cmlt v0.4s, v0.4s, #0
150+
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
153151
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
154152
; CHECK-NEXT: ret
155153
%add = select <4 x i1> %cond, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i32> <i32 0, i32 0, i32 0, i32 0>

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