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[RISCV][GISel] Remove s32 as a legal type for G_SMUL on RV64.
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9 files changed

+129
-136
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9 files changed

+129
-136
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‎llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -414,9 +414,9 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
414414

415415
if (ST.hasStdExtZmmul()) {
416416
getActionDefinitionsBuilder(G_MUL)
417-
.legalFor({s32, sXLen})
417+
.legalFor({sXLen})
418418
.widenScalarToNextPow2(0)
419-
.clampScalar(0, s32, sXLen);
419+
.clampScalar(0, sXLen, sXLen);
420420

421421
// clang-format off
422422
getActionDefinitionsBuilder({G_SMULH, G_UMULH})

‎llvm/lib/Target/RISCV/RISCVGISel.td

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -238,14 +238,6 @@ def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
238238
(SRLI (i64 (SLLI GPR:$rs, 32)), (ImmSubFrom32 uimm5:$shamt))>;
239239
}
240240

241-
//===----------------------------------------------------------------------===//
242-
// M RV64 i32 legalization patterns.
243-
//===----------------------------------------------------------------------===//
244-
245-
let Predicates = [HasStdExtZmmul, IsRV64] in {
246-
def : PatGprGpr<mul, MULW, i32, i32>;
247-
}
248-
249241
//===----------------------------------------------------------------------===//
250242
// Zb* RV64 i32 patterns not used by SelectionDAG.
251243
//===----------------------------------------------------------------------===//

‎llvm/test/CodeGen/RISCV/GlobalISel/alu-roundtrip.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -333,7 +333,7 @@ define i32 @mul_i32(i32 %a, i32 %b) {
333333
;
334334
; RV64IM-LABEL: mul_i32:
335335
; RV64IM: # %bb.0: # %entry
336-
; RV64IM-NEXT: mulw a0, a0, a1
336+
; RV64IM-NEXT: mul a0, a0, a1
337337
; RV64IM-NEXT: ret
338338
entry:
339339
%0 = mul i32 %a, %b

‎llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll

Lines changed: 8 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -3,30 +3,20 @@
33
; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
44

55
define i32 @freeze_int(i32 %x) {
6-
; RV32-LABEL: freeze_int:
7-
; RV32: # %bb.0:
8-
; RV32-NEXT: mul a0, a0, a0
9-
; RV32-NEXT: ret
10-
;
11-
; RV64-LABEL: freeze_int:
12-
; RV64: # %bb.0:
13-
; RV64-NEXT: mulw a0, a0, a0
14-
; RV64-NEXT: ret
6+
; CHECK-LABEL: freeze_int:
7+
; CHECK: # %bb.0:
8+
; CHECK-NEXT: mul a0, a0, a0
9+
; CHECK-NEXT: ret
1510
%y1 = freeze i32 %x
1611
%t1 = mul i32 %y1, %y1
1712
ret i32 %t1
1813
}
1914

2015
define i5 @freeze_int2(i5 %x) {
21-
; RV32-LABEL: freeze_int2:
22-
; RV32: # %bb.0:
23-
; RV32-NEXT: mul a0, a0, a0
24-
; RV32-NEXT: ret
25-
;
26-
; RV64-LABEL: freeze_int2:
27-
; RV64: # %bb.0:
28-
; RV64-NEXT: mulw a0, a0, a0
29-
; RV64-NEXT: ret
16+
; CHECK-LABEL: freeze_int2:
17+
; CHECK: # %bb.0:
18+
; CHECK-NEXT: mul a0, a0, a0
19+
; CHECK-NEXT: ret
3020
%y1 = freeze i5 %x
3121
%t1 = mul i5 %y1, %y1
3222
ret i5 %t1

‎llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir

Lines changed: 0 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -2,33 +2,6 @@
22
# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
33
# RUN: | FileCheck -check-prefix=RV64I %s
44

5-
---
6-
name: mul_i32
7-
legalized: true
8-
regBankSelected: true
9-
tracksRegLiveness: true
10-
body: |
11-
bb.0.entry:
12-
liveins: $x10, $x11
13-
14-
; RV64I-LABEL: name: mul_i32
15-
; RV64I: liveins: $x10, $x11
16-
; RV64I-NEXT: {{ $}}
17-
; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18-
; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19-
; RV64I-NEXT: [[MULW:%[0-9]+]]:gpr = MULW [[COPY]], [[COPY1]]
20-
; RV64I-NEXT: $x10 = COPY [[MULW]]
21-
; RV64I-NEXT: PseudoRET implicit $x10
22-
%0:gprb(s64) = COPY $x10
23-
%1:gprb(s32) = G_TRUNC %0(s64)
24-
%2:gprb(s64) = COPY $x11
25-
%3:gprb(s32) = G_TRUNC %2(s64)
26-
%4:gprb(s32) = G_MUL %1, %3
27-
%5:gprb(s64) = G_ANYEXT %4(s32)
28-
$x10 = COPY %5(s64)
29-
PseudoRET implicit $x10
30-
31-
...
325
---
336
name: sdiv_i32
347
legalized: true

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctlz-rv64.mir

Lines changed: 44 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -45,12 +45,16 @@ body: |
4545
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
4646
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
4747
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
48-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]]
49-
; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
48+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND8]](s32)
49+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
50+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
51+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
52+
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
53+
; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C7]](s32)
5054
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
5155
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]]
52-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
53-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
56+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
57+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
5458
; RV64I-NEXT: PseudoRET implicit $x10
5559
;
5660
; RV64ZBB-LABEL: name: ctlz_i8
@@ -120,13 +124,16 @@ body: |
120124
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
121125
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
122126
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
123-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
124-
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
127+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND9]](s32)
128+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
129+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
130+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
131+
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
125132
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
126133
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
127134
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
128-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
129-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
135+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
136+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
130137
; RV64I-NEXT: PseudoRET implicit $x10
131138
;
132139
; RV64ZBB-LABEL: name: ctlz_i16
@@ -192,12 +199,15 @@ body: |
192199
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
193200
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
194201
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
195-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]]
196-
; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)
202+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
203+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
204+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
205+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
206+
; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C9]](s32)
197207
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
198208
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]]
199-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
200-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
209+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
210+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
201211
; RV64I-NEXT: PseudoRET implicit $x10
202212
;
203213
; RV64ZBB-LABEL: name: ctlz_i32
@@ -319,12 +329,16 @@ body: |
319329
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
320330
; RV64I-NEXT: [[AND8:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
321331
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
322-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND8]], [[C]]
323-
; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
332+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND8]](s32)
333+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
334+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
335+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
336+
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
337+
; RV64I-NEXT: [[LSHR6:%[0-9]+]]:_(s32) = G_LSHR [[AND9]], [[C7]](s32)
324338
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
325339
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C8]], [[LSHR6]]
326-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
327-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
340+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
341+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
328342
; RV64I-NEXT: PseudoRET implicit $x10
329343
;
330344
; RV64ZBB-LABEL: name: ctlz_zero_undef_i8
@@ -394,13 +408,16 @@ body: |
394408
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 3855
395409
; RV64I-NEXT: [[AND9:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
396410
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
397-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND9]], [[C8]]
398-
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
411+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND9]](s32)
412+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
413+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
414+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
415+
; RV64I-NEXT: [[AND10:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
399416
; RV64I-NEXT: [[LSHR7:%[0-9]+]]:_(s32) = G_LSHR [[AND10]], [[C4]](s32)
400417
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
401418
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C9]], [[LSHR7]]
402-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
403-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
419+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
420+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
404421
; RV64I-NEXT: PseudoRET implicit $x10
405422
;
406423
; RV64ZBB-LABEL: name: ctlz_zero_undef_i16
@@ -466,12 +483,15 @@ body: |
466483
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C7]]
467484
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
468485
; RV64I-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
469-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C8]]
470-
; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C9]](s32)
486+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
487+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C8]](s32)
488+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
489+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
490+
; RV64I-NEXT: [[LSHR8:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C9]](s32)
471491
; RV64I-NEXT: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 32
472492
; RV64I-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[C10]], [[LSHR8]]
473-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
474-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
493+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB1]](s32)
494+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
475495
; RV64I-NEXT: PseudoRET implicit $x10
476496
;
477497
; RV64ZBB-LABEL: name: ctlz_zero_undef_i32

‎llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-ctpop-rv64.mir

Lines changed: 22 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -36,10 +36,14 @@ body: |
3636
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 15
3737
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
3838
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
39-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C]]
40-
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
41-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
42-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
39+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND5]](s32)
40+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C]](s32)
41+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
42+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
43+
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
44+
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C7]](s32)
45+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
46+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
4347
; RV64I-NEXT: PseudoRET implicit $x10
4448
;
4549
; RV64ZBB-LABEL: name: ctpop_i8
@@ -93,11 +97,14 @@ body: |
9397
; RV64I-NEXT: [[AND5:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C6]]
9498
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 257
9599
; RV64I-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
96-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND5]], [[C7]]
97-
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[MUL]], [[C1]]
100+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND5]](s32)
101+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C7]](s32)
102+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
103+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
104+
; RV64I-NEXT: [[AND6:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C1]]
98105
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[AND6]], [[C8]](s32)
99-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
100-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
106+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
107+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
101108
; RV64I-NEXT: PseudoRET implicit $x10
102109
;
103110
; RV64ZBB-LABEL: name: ctpop_i16
@@ -147,10 +154,13 @@ body: |
147154
; RV64I-NEXT: [[AND3:%[0-9]+]]:_(s32) = G_AND [[ADD1]], [[C5]]
148155
; RV64I-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 16843009
149156
; RV64I-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
150-
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[AND3]], [[C6]]
151-
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[MUL]], [[C7]](s32)
152-
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
153-
; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
157+
; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[AND3]](s32)
158+
; RV64I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[C6]](s32)
159+
; RV64I-NEXT: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[ANYEXT]], [[ANYEXT1]]
160+
; RV64I-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[MUL]](s64)
161+
; RV64I-NEXT: [[LSHR3:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC1]], [[C7]](s32)
162+
; RV64I-NEXT: [[ANYEXT2:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR3]](s32)
163+
; RV64I-NEXT: $x10 = COPY [[ANYEXT2]](s64)
154164
; RV64I-NEXT: PseudoRET implicit $x10
155165
;
156166
; RV64ZBB-LABEL: name: ctpop_i32

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